MTB50P03HDL
Preferred Device
Power MOSFET
50 Amps, 30 Volts, Logic Level
P−Channel D
2
PAK
This Power MOSFET is designed to withstand high energy in the
avalanche and commutation modes. The energy efficient design also
offers a drain−to−source diode with a fast recovery time. Designed for
low voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.
Features
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50 AMPERES
30 VOLTS
R
DS(on)
= 25 mW
P−Channel
D
•
Avalanche Energy Specified
•
Source−to−Drain Diode Recovery Time Comparable to a
•
•
•
•
•
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
I
DSS
and V
DS(on)
Specified at Elevated Temperature
Short Heatsink Tab Manufactured − Not Sheared
Specially Designed Leadframe for Maximum Power Dissipation
Pb−Free Packages are Available
G
S
4
D
2
PAK
CASE 418B
STYLE 2
MAXIMUM RATINGS
(T
C
= 25°C unless otherwise noted)
Rating
Drain−Source Voltage
Drain−Gate Voltage (R
GS
= 1.0 MW)
Gate−Source Voltage
− Continuous
− Non−Repetitive (t
p
≤
10 ms)
Drain Current − Continuous
Drain Current
− Continuous @ 100°C
Drain Current
− Single Pulse (t
p
≤
10
ms)
Total Power Dissipation
Derate above 25°C
Total Power Dissipation @ T
C
= 25°C, when
mounted with the minimum recommended pad size
Operating and Storage Temperature Range
Single Pulse Drain−to−Source Avalanche
Energy − Starting T
J
= 25°C
(V
DD
= 25 Vdc, V
GS
= 5.0 Vdc, Peak
I
L
= 50 Apk, L = 1.0 mH, R
G
= 25
W)
Thermal Resistance
− Junction−to−Case
− Junction−to−Ambient
− Junction−to−Ambient, when mounted with the
minimum recommended pad size
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds
Symbol
V
DSS
V
DGR
V
GS
V
GSM
I
D
I
D
I
DM
P
D
Value
30
30
±15
±
20
50
31
150
125
1.0
2.5
− 55 to
150
1250
Unit
Vdc
Vdc
Vdc
Vpk
Adc
Apk
W
W/°C
W
°C
mJ
1
Gate
MTB50P03H
A
Y
WW
G
1
2
3
MARKING DIAGRAM
& PIN ASSIGNMENT
4
Drain
M
TB
50P03HG
AYWW
T
J
, T
stg
E
AS
2
Drain
3
Source
°C/W
R
qJC
R
qJA
R
qJA
T
L
1.0
62.5
50
260
°C
= Device Code
= Assembly Location
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
Preferred
devices are recommended choices for future use
and best overall value.
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
©
Semiconductor Components Industries, LLC, 2006
1
June, 2006 − Rev. 6
Publication Order Number:
MTB50P03HDL/D
MTB50P03HDL
ELECTRICAL CHARACTERISTICS
(T
J
= 25°C unless otherwise noted)
Characteristic
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
(V
GS
= 0 Vdc, I
D
= 250
mAdc)
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
(V
DS
= 30 Vdc, V
GS
= 0 Vdc)
(V
DS
= 30 Vdc, V
GS
= 0 Vdc, T
J
= 125°C)
Gate−Body Leakage Current
(V
GS
=
±15
Vdc, V
DS
= 0 Vdc)
ON CHARACTERISTICS
(Note 1)
Gate Threshold Voltage
(V
DS
= V
GS
, I
D
= 250
mAdc)
Threshold Temperature Coefficient (Negative)
Static Drain−Source On−Resistance
(V
GS
= 5.0 Vdc, I
D
= 25 Adc)
Drain−Source On−Voltage (V
GS
= 5.0 Vdc)
(I
D
= 50 Adc)
(I
D
= 25 Adc, T
J
=125°C)
Forward Transconductance
(V
DS
= 5.0 Vdc, I
D
= 25 Adc)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Transfer Capacitance
SWITCHING CHARACTERISTICS
(Note 2)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Gate Charge (See Figure 8)
(V
DS
= 24 Vdc, I
D
= 50 Adc,
V
GS
= 5.0 Vdc)
(V
DD
= 15 Vdc, I
D
= 50 Adc,
V
GS
= 5.0 Vdc, R
G
= 2.3
W)
t
d(on)
t
r
t
d(off)
t
f
Q
T
Q
1
Q
2
Q
3
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage
(I
S
= 50 Adc, V
GS
= 0 Vdc)
(I
S
= 50 Adc, V
GS
= 0 Vdc, T
J
= 125°C)
V
SD
−
−
t
rr
(I
S
= 50 Adc, V
GS
= 0 Vdc,
dI
S
/dt = 100 A/ms)
Reverse Recovery Stored Charge
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25″ from package to center of die)
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
1. Pulse Test: Pulse Width
≤
300
ms,
Duty Cycle
≤
2%.
2. Switching characteristics are independent of operating junction temperature.
3. Reflects typical values.
Max limit − Typ
C
pk
=
3 x SIGMA
L
D
L
S
−
−
3.5
7.5
−
−
nH
nH
t
a
t
b
Q
RR
−
−
−
−
2.39
1.84
106
58
48
0.246
3.0
−
−
−
−
−
mC
ns
Vdc
−
−
−
−
−
−
−
−
22
340
90
218
74
13.6
44.8
35
30
466
117
300
100
−
−
−
nC
ns
(V
DS
= 25 Vdc, V
GS
= 0 Vdc, f = 1.0 MHz)
C
iss
C
oss
C
rss
−
−
−
3500
1550
550
4900
2170
770
pF
(C
pk
≥
3.0) (Note 3)
V
GS(th)
1.0
−
(C
pk
≥
3.0) (Note 3)
R
DS(on)
−
V
DS(on)
−
−
g
FS
15
20
−
0.83
−
1.5
1.3
mhos
20.9
25
Vdc
1.5
4.0
2.0
−
Vdc
mV/°C
mW
(C
pk
≥
2.0) (Note 3)
V
(BR)DSS
30
−
I
DSS
−
−
I
GSS
−
−
100
−
−
1.0
10
nAdc
−
26
−
−
Vdc
mV/°C
mAdc
Symbol
Min
Typ
Max
Unit
Reverse Recovery Time
(See Figure 15)
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MTB50P03HDL
TYPICAL ELECTRICAL CHARACTERISTICS
100
I D , DRAIN CURRENT (AMPS)
100
V
GS
= 10 V
8V
80
4.5 V
6V
4V
5V
I D , DRAIN CURRENT (AMPS)
80
T
J
= 25°C
V
DS
≥
5 V
T
J
= − 55°C
25°C
100°C
60
60
3.5 V
40
3V
20
2.5 V
0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
40
20
0
1.5
1.9
2.3
2.7
3.1
3.5
3.9
4.3
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
Figure 2. Transfer Characteristics
0.029
V
GS
= 5 V
0.027
0.025
0.023
25°C
0.021
0.019
0.017
0.015
0
20
40
− 55°C
T
J
= 100°C
0.022
T
J
= 25°C
0.021
0.020
0.019
0.018
0.017
10 V
0.016
0.015
0
20
40
60
80
100
V
GS
= 5 V
60
80
100
I
D
, DRAIN CURRENT (AMPS)
I
D
, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance versus Drain Current
and Temperature
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
RDS(on) , DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
1.35
V
GS
= 5 V
I
D
= 25 A
I DSS, LEAKAGE (nA)
1000
V
GS
= 0 V
1.25
T
J
= 125°C
100
1.15
1.05
0.95
100°C
0.85
− 50
10
− 25
0
25
50
75
100
125
150
0
5
10
15
20
25
30
T
J
, JUNCTION TEMPERATURE (°C)
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage
Current versus Voltage
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MTB50P03HDL
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I
G(AV)
) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a
resistive load, V
GS
remains virtually constant at a level
known as the plateau voltage, V
SGP
. Therefore, rise and fall
times may be approximated by the following:
t
r
= Q
2
x R
G
/(V
GG
− V
GSP
)
t
f
= Q
2
x R
G
/V
GSP
where
V
GG
= the gate drive voltage, which varies from zero to V
GG
R
G
= the gate drive resistance
and Q
2
and V
GSP
are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
d(on)
= R
G
C
iss
In [V
GG
/(V
GG
− V
GSP
)]
t
d(off)
= R
G
C
iss
In (V
GG
/V
GSP
)
The capacitance (C
iss
) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
calculating t
d(on)
and is read at a voltage corresponding to the
on−state when calculating t
d(off)
.
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring which
is common to both the drain and gate current paths, produces
a voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a
function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also complicates
the mathematics. And finally, MOSFETs have finite internal
gate resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to
measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
14000
V
DS
= 0 V
12000 C
iss
V
GS
= 0 V
T
J
= 25°C
C, CAPACITANCE (pF)
10000
8000
C
rss
6000
4000
2000
0
10
5
V
GS
0
V
DS
5
C
iss
C
oss
C
rss
10
15
20
25
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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4
MTB50P03HDL
6
QT
5
Q1
4
3
2
1
Q3
0
0
10
20
30
40
50
60
V
DS
70
Q
T
, TOTAL GATE CHARGE (nC)
I
D
= 50 A
T
J
= 25°C
Q2
V
GS
25
20
15
10
5
0
80
30
VDS , DRAIN−TO−SOURCE VOLTAGE (VOLTS)
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
1000
V
DD
= 30 V
V
GS
= 10 V
I
D
= 50 A
T
J
= 25°C
t
r
t
f
t, TIME (ns)
t
d(off)
100
t
d(on)
10
1
R
G
, GATE RESISTANCE (Ohms)
10
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse
recovery characteristics which play a major role in
determining switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier
device, therefore it has a finite reverse recovery time, t
rr
, due
to the storage of minority carrier charge, Q
RR
, as shown in
the typical reverse recovery wave form of Figure 12. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery
further increases switching losses. Therefore, one would
like a diode with short t
rr
and low Q
RR
specifications to
minimize these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current
ringing. The mechanisms at work are finite irremovable
circuit parasitic inductances and capacitances acted upon by
50
I S , SOURCE CURRENT (AMPS)
V
GS
= 0 V
T
J
= 25°C
40
high di/dts. The diode’s negative di/dt during t
a
is directly
controlled by the device clearing the stored charge.
However, the positive di/dt during t
b
is an uncontrollable
diode characteristic and is usually the culprit that induces
current ringing. Therefore, when comparing diodes, the
ratio of t
b
/t
a
serves as a good indicator of recovery
abruptness and thus gives a comparative estimate of
probable noise generated. A ratio of 1 is considered ideal and
values less than 0.5 are considered snappy.
Compared to ON Semiconductor standard cell density
low voltage MOSFETs, high cell density MOSFET diodes
are faster (shorter t
rr
), have less stored charge and a softer
reverse recovery characteristic. The softness advantage of
the high cell density diode means they can be forced through
reverse recovery at a higher di/dt than a standard cell
MOSFET diode without increasing the current ringing or the
noise generated. In addition, power dissipation incurred
from switching the diode will be less due to the shorter
recovery time and lower switching losses.
30
20
10
0
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
V
SD
, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
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