SAF1761
Hi-Speed Universal Serial Bus On-The-Go controller
Rev. 2 — 19 June 2012
Product data sheet
1. General description
The SAF1761 is a single-chip Hi-Speed Universal Serial Bus (USB) On-The-Go (OTG)
Controller integrated with advanced NXP slave host controller and the peripheral
controller.
The Hi-Speed USB host controller and peripheral controller comply to
Ref. 1 “Universal
Serial Bus Specification Rev. 2.0”
and support data transfer speeds of up to 480 Mbit/s.
The Enhanced Host Controller Interface (EHCI) core implemented in the host controller is
adapted from
Ref. 2 “Enhanced Host Controller Interface Specification for Universal Serial
Bus Rev. 1.0”.
The OTG controller adheres to
Ref. 3 “On-The-Go Supplement to the USB
Specification Rev. 1.3”.
The SAF1761 has three USB ports. Port 1 can be configured to function as a downstream
port, an upstream port or an OTG port; ports 2 and 3 are always configured as
downstream ports. The OTG port can switch its role from host to peripheral, and
peripheral to host. The OTG port can become a host through the Host Negotiation
Protocol (HNP) as specified in the OTG supplement.
2. Features and benefits
Automotive qualified in accordance with AEC-Q100
Compliant with
Ref. 1 “Universal Serial Bus Specification Rev. 2.0”;
supporting data
transfer at high-speed (480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s)
Integrated Transaction Translator (TT) for original USB (full-speed and low-speed)
peripheral support
Three USB ports that support three operational modes:
Mode 1: Port 1 is an OTG controller port, and ports 2 and 3 are host controller ports
Mode 2: Ports 1, 2 and 3 are host controller ports
Mode 3: Port 1 is a peripheral controller port, and ports 2 and 3 are host controller
ports
Supports OTG Host Negotiation Protocol (HNP) and Session Request Protocol (SRP)
Multitasking support with virtual segmentation feature (up to four banks)
High-speed memory controller (variable latency and SRAM external interface)
Directly addressable memory architecture
Generic processor interface to most CPUs, such as Hitachi SH-3 and SH-4, NXP XA,
Intel StrongARM, NEC and Toshiba MIPS, Freescale DragonBall and PowerPC
Reduced Instruction Set Computer (RISC) processors
Configurable 32-bit and 16-bit external memory data bus
Supports Programmed I/O (PIO) and Direct Memory Access (DMA)
Slave DMA implementation on CPU interface to reduce the host systems CPU load
NXP Semiconductors
SAF1761
Hi-Speed USB OTG controller
Separate IRQ, DREQ and DACK lines for the host controller and the peripheral
controller
Integrated multi-configuration FIFO
Double-buffering scheme increases throughput and facilitates real-time data transfer
Integrated Phase-Locked Loop (PLL) with external 12 MHz crystal for low
ElectroMagnetic Interference (EMI)
Tolerant I/O for low voltage CPU interface (1.65 V to 3.3 V)
3.3 V-to-5.0 V external power supply input
Integrated 5.0 V-to-1.8 V or 3.3 V-to-1.8 V voltage regulator (internal 1.8 V for
low-power core)
Internal power-on reset or low-voltage reset and block-dedicated software reset
Supports suspend and remote wake-up
Built-in overcurrent circuitry (analog overcurrent protection)
Hybrid-power mode: V
CC(5V0)
(can be switched off), V
CC(I/O)
(permanent)
Target total current consumption:
Normal operation; one port in high-speed active: I
CC
< 100 mA when the internal
charge pump is not used
Suspend mode: I
CC(susp)
< 150
μA
at ambient temperature of +25
°C
Host controller-specific features
High performance USB host with integrated Hi-Speed USB transceivers; supports
high-speed, full-speed and low-speed
EHCI core is adapted from
Ref. 2 “Enhanced Host Controller Interface
Specification for Universal Serial Bus Rev. 1.0”
Configurable power management
Integrated TT for Original USB peripheral support on all three ports
Integrated 64 kB high-speed memory (internally organized as 8 k
×
64 bit)
Additional 2.5 kB separate memory for TT
Individual or global overcurrent protection with built-in sense circuits
Built-in overcurrent circuitry (digital or analog overcurrent protection)
OTG controller-specific features
OTG transceiver: fully integrated; adheres to
Ref. 3 “On-The-Go Supplement to the
USB Specification Rev. 1.3”
Supports HNP and SRP for OTG dual-role devices
HNP: status and control registers for software implementation
SRP: status and control registers for software implementation
Programmable timers with high resolution (0.01 ms to 80 ms) for HNP and SRP
Supports external source of V
BUS
Peripheral controller-specific features
High-performance USB peripheral controller with integrated Serial Interface Engine
(SIE), FIFO memory and transceiver
Complies with
Ref. 1 “Universal Serial Bus Specification Rev. 2.0”
and most device
class specifications
Supports auto Hi-Speed USB mode discovery and Original USB fallback
capabilities
Supports high-speed and full-speed on the peripheral controller
Bus-powered or self-powered capability with suspend mode
SAF1761
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 19 June 2012
2 of 165
NXP Semiconductors
SAF1761
Hi-Speed USB OTG controller
Slave DMA, fully autonomous and supports multiple configurations
Seven IN endpoints, seven OUT endpoints and one fixed control IN and OUT
endpoint
Integrated 8 kB memory
Software-controllable connection to the USB bus, SoftConnect
3. Applications
The SAF1761 can be used to implement a dual-role USB device, USB host or USB
peripheral, depending on the cable connection. If the dual-role device is connected to a
typical USB peripheral, it behaves like a typical USB host. The dual-role device can also
be connected to a PC or any other USB host and behave like a typical USB peripheral.
This NXP USB product can only be used in automotive applications. Inclusion or use of
the NXP USB products in other than automotive applications is not permitted and for your
company’s own risk. Your company agrees to full indemnify NXP for any damages
resulting from such inclusion or use.
4. Ordering information
Table 1.
Ordering information
Package
Name
SAF1761BE
LQFP128
Description
plastic low profile quad flat package; 128 leads; body 14
×
20
×
1.4 mm
Version
SOT425-1
Type number
SAF1761
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 19 June 2012
3 of 165
NXP Semiconductors
SAF1761
Hi-Speed USB OTG controller
5. Block diagram
V
CC(I/O)
37 to 39, 41 to 43,
45 to 47, 49, 51,
52, 54, 56 to 58,
60 to 62, 64 to 66,
68 to 70, 72 to 74,
76 to 78, 80
DATA[15:0]/DATA[31:0]
82, 84, 86, 87,
89, 91 to 93,
95 to 98,
100 to 103, 105
A[17:1]
CS_N
RD_N
WR_N
DC_IRQ
HC_IRQ
DC_DREQ
HC_DREQ
HC_DACK
DC_DACK
106
107
108
111
112
113
114
116
117
REGISTERS
SUPPORT
124
125
126
CHARGE
PUMP
TRANSACTION
TRANSLATOR
(TT) AND RAM
ADVANCED
NXP
SLAVE HOST
CONTROLLER
ADVANCED
PERIPHERAL
CONTROLLER
5, 50,
85, 118
5 V-TO-1.8 V
VOLTAGE
REGULATOR
REG1V8
6, 7
V
CC(5V0)
10, 40, 48, 59, 67,
75, 83, 94, 104, 115
SAF1761BE
PLL
SEL16/32
HC PTD
MEMORY
(3 kB)
HC PAYLOAD
MEMORY
(60 kB)
DC BUFFER
MEMORY
8 KBYTES
GLOBAL CONTROL
AND POWER
MANAGEMENT
30 MHz
60 MHz
11
12
13
XTAL1
XTAL2
CLKIN
GENERIC PROCESSOR BUS
BUS INTERFACE:
MEMORY
MANAGEMENT
UNIT
+
SLAVE DMA
CONTROLLER
+
INTERRUPT
CONTROL
122
119
120
17
RESET_N
HC_SUSPEND/
WAKEUP_N
DC_SUSPEND/
WAKEUP_N
MEMORY ARBITER
AND FIFO
POWER-ON
RESET AND
V
BAT
ON
110
BAT_ON_N
C_B
C_A
V
CC(C_IN)
5 V-TO-3.3 V
VOLTAGE
REGULATOR
9
REG3V3
OTG CONTROLLER
DYNAMIC PORT ROUTING AND PORT CONTROL LOGIC
DIGITAL
AND ANALOG
OVERCURRENT
PROTECTION
2
REF5V
GND(OSC)
8
HI-SPEED
USB ATX1
HI-SPEED
USB ATX2
HI-SPEED
USB ATX3
3
4, 17, 24,
31, 123
53, 88, 121
14, 36, 44, 55, 63,
71, 79, 90, 99, 109
001aai626
ID
GNDA
GNDC
16 15 20 19 18
RREF1
DP1
DM1
21 127
23 22 27 26 25
DP2
DM2
28 128 30 29 34 33 32 35 1
RREF3
DP3
DM3
OC3_N
PSW3_N
RREF2
GNDD
GND GNDA
(RREF1)
OC1_N/ GND GNDA
V
BUS
(RREF2)
PSW1_N
OC2_N GND GNDA
(RREF3)
PSW2_N
All ground pins should normally be connected to a common ground plane.
Fig 1.
Block diagram
SAF1761
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 19 June 2012
4 of 165
NXP Semiconductors
SAF1761
Hi-Speed USB OTG controller
6. Pinning information
6.1 Pinning
128
103
102
1
SAF1761BE
38
39
64
65
001aai627
Fig 2.
Pin configuration (LQFP128); top view
6.2 Pin description
Table 2.
Pin description
Pin
LQFP128
OC3_N
1
AI/I
port 3 analog (5 V input) and digital overcurrent input; if not used, connect to
V
CC(I/O)
through a 10 kΩ resistor
input, 5 V tolerant
REF5V
ID
2
3
AI
I
5 V reference input for analog OC detector; connect a 100 nF decoupling capacitor
ID input to detect the default host or peripheral setting when port 1 is in OTG mode;
pull-up to 3.3 V through a 4.7 kΩ resistor
input, 3.3 V tolerant
GNDA
REG1V8
4
5
G
P
analog ground
core power output (1.8 V); internal 1.8 V for the digital core; used for decoupling;
connect a 100 nF capacitor; for details on additional capacitor placement, see
Section 7.8
input to internal regulators (3.0 V-to-5.5 V); connect a 100 nF decoupling capacitor;
see
Section 7.8
input to internal regulators (3.0 V-to-5.5 V); connect a 100 nF decoupling capacitor;
see
Section 7.8
oscillator ground
regulator output (3.3 V); for decoupling only; connect a 100 nF capacitor and a
4.7
μF-to-10 μF
capacitor; see
Section 7.8
digital supply voltage; 1.65 V to 3.6 V; connect a 100 nF decoupling capacitor; see
Section 7.8
12 MHz crystal connection input; connect to ground if an external clock is used
12 MHz crystal connection output
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Symbol
[1][2]
Type
[3]
Description
V
CC(5V0)
V
CC(5V0)
GND(OSC)
REG3V3
V
CC(I/O)
XTAL1
XTAL2
SAF1761
6
7
8
9
10
11
12
P
P
G
P
P
AI
AO
Product data sheet
Rev. 2 — 19 June 2012
5 of 165
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