®
HIP6004E
Data Sheet
July 2004
FN4997.2
Buck and Synchronous-Rectifier (PWM)
Controller and Output Voltage Monitor
The HIP6004E provides complete control and protection for a
DC-DC converter optimized for high-performance
microprocessor applications. It is designed to drive two
N-Channel MOSFETs in a synchronous-rectified buck topology.
The HIP6004E integrates all of the control, output adjustment,
monitoring and protection functions into a single package.
The output voltage of the converter is easily adjusted and
precisely regulated. The HIP6004E includes a 5-input digital-
to-analog converter (DAC) that adjusts the output voltage
from 1.05V
DC
to 1.825V
DC
in 25mV increments steps. The
precision reference and voltage-mode regulator hold the
selected output voltage to within
±1%
over temperature and
line voltage variations.
The HIP6004E provides simple, single feedback loop,
voltage-mode control with fast transient response. It includes
a 200kHz free-running triangle-wave oscillator that is
adjustable from below 50kHz to over 1MHz. The error
amplifier features a 15MHz gain-bandwidth product and
6V/µs slew rate which enables high converter bandwidth for
fast transient performance. The resulting PWM duty ratio
ranges from 0% to 100%.
The HIP6004E monitors the output voltage with a window
comparator that tracks the DAC output and issues a Power
Good signal when the output is within
±10%.
The HIP6004E
protects against over-current and overvoltage conditions by
inhibiting PWM operation. Additional built-in overvoltage
protection triggers an external SCR to crowbar the input
supply. The HIP6004E monitors the current by using the
r
DS(ON)
of the upper MOSFET which eliminates the need for
a current sensing resistor.
Features
• Drives two N-Channel MOSFETs
• Operates from +5V or +12V Input
• Simple single-loop control design
- Voltage-mode PWM control
• Fast transient response
- High-bandwidth error amplifier
- Full 0% to 100% Duty Ratio
• Excellent output voltage regulation
-
±1%
Over Line Voltage and Temperature
• 5-Bit digital-to-analog output
Voltage Selection
- 25mV binary steps . . . . . . . . . . . 1.05V
DC
to 1.825V
DC
• Power good output voltage monitor
• Overvoltage and overcurrent fault monitors
- Does not require extra current sensing element,
Uses MOSFET’s r
DS(ON)
• Small Converter Size
- Constant Frequency Operation
- 200kHz Free-Running Oscillator Programmable from
50kHz to over 1MHz
• Pb-free available
Applications
• VRM8.5 modules for Pentium III and Other
Microprocessors
• High-Power DC-DC Regulators
• Low-Voltage Distributed Power Supplies
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
Pinout
HIP6004E
TOP VIEW
VSEN
OCSET
SS
VID25mV
VID0
VID1
VID2
VID3
COMP
1
2
3
4
5
6
7
8
9
20 RT
19 OVP
18 VCC
17 LGATE
16 PGND
15 BOOT
14 UGATE
13 PHASE
12 PGOOD
11 GND
Ordering Information
PART NUMBER
HIP6004ECB
HIP6004ECBZ
(See Note)
HIP6004ECV
HIP6004ECVZ
(See Note)
TEMP.
RANGE (
o
C)
0 to 70
0 to 70
0 to 70
0 to 70
PACKAGE
20 Ld SOIC
20 Ld SOIC
(Pb-free)
20 Ld TSSOP
20 Ld TSSOP
(Pb-free)
PKG.
DWG. #
M20.3
M20.3
M20.173
M20.173
*Add “-T” suffix to part number for tape and reel packaging.
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding
compounds/die attach materials and 100% matte tin plate termination finish, which
is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that meet or
exceed the Pb-free requirements of IPC/JEDEC J Std-020B.
FB 10
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2001, 2004. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
HIP6004E
Typical Application
+12V
VCC
V
IN
= +5V OR +12V
OCSET
BOOT
OSC
HIP6004E
PGOOD
SS
OVP
RT
VID25mV
VID0
VID1
VID2
VID3
FB
MONITOR AND
PROTECTION
UGATE
PHASE
+V
OUT
D/A
+
+
-
LGATE
PGND
VSEN
GND
-
COMP
Block Diagram
VCC
VSEN
110%
+
POWER-ON
RESET (POR)
-
-
-
-
PGOOD
90%
+
115%
+
SOFT-
START
OVER-
CURRENT
4V
OVER-
VOLTAGE
10µA
OVP
SS
BOOT
UGATE
PHASE
VID25mV
VID0
VID1
VID2
VID3
FB
COMP
RT
OSCILLATOR
D/A
CONVERTER
(DAC)
DACOUT
+
PWM
COMPARATOR
GATE
INHIBIT CONTROL
LOGIC
PWM
LGATE
PGND
GND
+
OCSET
REFERENCE
200µA
-
+
-
ERROR
AMP
2
HIP6004E
Absolute Maximum Ratings
Supply voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+15V
Boot voltage, V
BOOT
- V
PHASE
. . . . . . . . . . . . . . . . . . . . . . . . .+15V
Input, output or I/O voltage . . . . . . . . . . . . GND -0.3V to V
CC
+0.3V
ESD classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2
Thermal Information
Thermal resistance (Typical, Note 1)
θ
JA
(
o
C/W)
Operating Conditions
Supply voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . +12V
±10%
Ambient temperature range . . . . . . . . . . . . . . . . . . . . . . 0
o
C to 70
o
C
SOIC package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
65
TSSOP package . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
Maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . 150
o
C
Maximum storage temperature range . . . . . . . . . . . -65
o
C to 150
o
C
Maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300
o
C
(lead tips only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on a high-effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
PARAMETER
VCC SUPPLY CURRENT
Nominal supply
POWER-ON RESET
Rising VCC threshold
Falling VCC threshold
Rising V
OCSET
threshold
OSCILLATOR
Free running frequency
Total variation
Ramp amplitude
REFERENCE AND DAC
Recommended operating conditions, unless otherwise noted
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
I
CC
UGATE and LGATE open
-
5
-
mA
V
OCSET
= 4.5V
V
OCSET
= 4.5V
-
8.2
-
-
-
1.26
10.4
-
-
V
V
V
RT = open
6kΩ < RT to GND < 200kΩ
∆V
OSC
RT = open
185
-15
-
200
-
1.9
215
+15
-
kHz
%
V
P-P
V
V
%
DAC (VID0-VID4) input low voltage
DAC (VID0-VID4) input high voltage
DACOUT voltage accuracy
ERROR AMPLIFIER
DC gain
Gain-bandwidth product
Slew rate
GATE DRIVERS
Upper gate source
Upper gate sink
Lower gate source
Lower gate sink
PROTECTION
Overvoltage trip (VSEN/DACOUT)
OCSET current source
OVP sourcing current
Soft start current
POWER GOOD
Upper threshold (VSEN/DACOUT)
Lower threshold (VSEN/DACOUT)
Hysteresis (VSEN/DACOUT)
PGOOD voltage low
V
PGOOD
VSEN rising
VSEN falling
Upper and lower threshold
I
PGOOD
= -5mA
I
OCSET
I
OVP
I
SS
V
OCSET
= 4.5V
DC
V
SEN
= 5.5V, V
OVP
= 0V
I
UGATE
R
UGATE
I
LGATE
R
LGATE
V
BOOT
- V
PHASE
= 12V, V
UGATE
= 6V
I
LGATE
= 0.3A
V
CC
= 12V, V
LGATE
= 6V
I
LGATE
= 0.3A
GBWP
SR
COMP = 10pF
-
2.0
-1.0
-
-
-
0.8
-
+1.0
-
-
-
88
15
6
-
-
-
dB
MHz
V/µs
350
-
300
-
500
5.5
450
3.5
-
10
-
6.5
mA
Ω
mA
Ω
-
170
60
-
115
200
-
10
120
230
-
-
%
µA
mA
µA
106
89
-
-
-
-
2
0.3
111
94
-
-
%
%
%
V
3
HIP6004E
Typical Performance Curves
80
70
1000
RESISTANCE (kΩ)
R
T
PULLUP
TO +12V
I
CC
(mA)
60
50
40
30
10
R
T
PULLDOWN TO V
SS
10
10
100
SWITCHING FREQUENCY (kHz)
1000
0
100
200
300
400
500
600
20
C
GATE
= 10pF
C
GATE
= 1000pF
C
UPPER
= C
LOWER
= C
GATE
C
GATE
= 3300pF
100
700
800
900
1000
SWITCHING FREQUENCY (kHz)
FIGURE 1. R
T
RESISTANCE vs FREQUENCY
FIGURE 2. BIAS SUPPLY CURRENT vs FREQUENCY
Functional Pin Descriptions
VSEN
OCSET
SS
VID25mV
VID0
VID1
VID2
VID3
COMP
1
2
3
4
5
6
7
8
9
20 RT
19 OVP
18 VCC
17 LGATE
16 PGND
15 BOOT
14 UGATE
13 PHASE
12 PGOOD
11 GND
reference (DACOUT). The level of DACOUT sets the
converter output voltage. It also sets the PGOOD and OVP
thresholds. Table 1 specifies DACOUT for the all
combinations of DAC inputs.
COMP (Pin 9) and FB (Pin 10)
COMP and FB are the available external pins of the error
amplifier. The FB pin is the inverting input of the error
amplifier and the COMP pin is the error amplifier output.
These pins are used to compensate the voltage-control
feedback loop of the converter.
GND (Pin 11)
Signal ground for the IC. All voltage levels are measured with
respect to this pin.
FB 10
VSEN (Pin 1)
This pin is connected to the converter’s output voltage. The
PGOOD and OVP comparator circuits use this signal to
report output voltage status and for overvoltage protection.
PGOOD (Pin 12)
PGOOD is an open collector output used to indicate the
status of the converter output voltage. This pin is pulled low
when the converter output is not within
±10%
of the
DACOUT reference voltage.
OCSET (Pin 2)
Connect a resistor (R
OCSET
) from this pin to the drain of the
upper MOSFET. R
OCSET
, an internal 200µA current source
(I
OCSET
), and the upper MOSFET on-resistance (r
DS(ON)
)
set the converter overcurrent (OC) trip point according to the
following equation:
I
OCSET
x R
OCSET
I
PEAK
= ----------------------------------------------------
-
r
DS
(
ON
)
PHASE (Pin 13)
Connect the PHASE pin to the upper MOSFET source. This
pin is used to monitor the voltage drop across the MOSFET
for overcurrent protection. This pin also provides the return
path for the upper gate drive.
UGATE (Pin 14)
Connect UGATE to the upper MOSFET gate. This pin
provides the gate drive for the upper MOSFET.
An over-current trip cycles the soft-start function.
SS (Pin 3)
Connect a capacitor from this pin to ground. This capacitor,
along with an internal 10µA current source, sets the soft-
start interval of the converter.
BOOT (Pin 15)
This pin provides bias voltage to the upper MOSFET driver.
A bootstrap circuit may be used to create a BOOT voltage
suitable to drive a standard N-Channel MOSFET.
VID25mV-VID3 (Pins 4-8)
VID25mV - VID3 are the input pins to the 5-bit DAC. The
states of these five pins program the internal voltage
4
HIP6004E
PGND (Pin 16)
This is the power ground connection. Tie the lower MOSFET
source to this pin.
the SS pin to 4V. Soft start clamps the error amplifier output
(COMP pin) and reference input (+ terminal of error amp) to the
SS pin voltage. Figure 3 shows the soft-start interval with
C
SS
= 0.1µF. Initially the clamp on the error amplifier (COMP
pin) controls the converter’s output voltage. At t
1
in Figure 3, the
SS voltage reaches the valley of the oscillator’s triangle wave.
The oscillator’s triangular waveform is compared to the ramping
error amplifier voltage. This generates PHASE pulses of
increasing width that charge the output capacitor(s). This
interval of increasing pulse width continues to t
2
. With sufficient
output voltage, the clamp on the reference input controls the
output voltage. This is the interval between t
2
and t
3
in Figure 3.
At t
3
the SS voltage exceeds the DACOUT voltage and the
output voltage is in regulation. This method provides a rapid
and controlled output voltage rise. The PGOOD signal toggles
‘high’ when the output voltage (VSEN pin) is within
±10%
of
DACOUT. The 2% hysteresis built into the power good
comparators prevents PGOOD oscillation due to nominal
output voltage ripple.
LGATE (Pin 17)
Connect LGATE to the lower MOSFET gate. This pin
provides the gate drive for the lower MOSFET.
VCC (Pin 18)
Provide a 12V bias supply for the chip to this pin.
OVP (Pin 19)
The OVP pin can be used to drive an external SCR in the
event of an overvoltage condition. Output rising 15% more
than the DAC-set voltage triggers a high output on this pin
and disables PWM gate drive circuitry.
RT (Pin 20)
This pin provides oscillator switching frequency adjustment.
By placing a resistor (R
T
) from this pin to GND, the nominal
200kHz switching frequency is increased according to the
following equation:
5 x 10
-
Fs
≈
200kHz
+ --------------------
R
T
(
kΩ
)
6
(R
T
to GND)
0V
PGOOD
(2V/DIV.)
Conversely, connecting a pull-up resistor (R
T
) from this pin to
V
CC
reduces the switching frequency according to the
following equation:
SOFT-START
(1V/DIV.)
OUTPUT
VOLTAGE
(1V/DIV.)
4 x 10
Fs
≈
200kHz
– --------------------
-
R
T
(
kΩ
)
7
0V
(R
T
to 12V)
0V
t
1
t
2
TIME (5ms/DIV.)
t
3
FIGURE 3. SOFT START INTERVAL
RT pin has a constant voltage of 1.26V typically.
Overcurrent Protection
The overcurrent function protects the converter from a shorted
output by using the upper MOSFET’s on-resistance, r
DS(ON)
to monitor the current. This method enhances the converter’s
efficiency and reduces cost by eliminating a current sensing
resistor.
Functional Description
Initialization
The HIP6004E automatically initializes upon receipt of power.
Special sequencing of the input supplies is not necessary. The
Power-On Reset (POR) function continually monitors the input
supply voltages. The POR monitors the bias voltage at the VCC
pin and the input voltage (V
IN
) on the OCSET pin. The level on
OCSET is equal to V
IN
less a fixed voltage drop (see over-
current protection). The POR function initiates soft-start
operation after both input supply voltages exceed their POR
thresholds. For operation with a single +12V power source, V
IN
and V
CC
are equivalent and the +12V power source must
exceed the rising VCC threshold before POR initiates operation.
Soft Start
The POR function initiates the soft-start sequence. An internal
10µA current source charges an external capacitor (C
SS
) on
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