INTEGRATED CIRCUITS
GTL16612
18-bit GTL/GTL
+
to LVTTL/TTL
bidirectional universal translator (3-State)
Product data
Supersedes data of 2000 Jun 19
2002 Dec 13
Philips
Semiconductors
Philips Semiconductors
Product specification
18-bit GTL/GTL
+
to LVTTL/TTL bidirectional
universal translator (3-State)
GTL16612
FEATURES
•
18-bit bidirectional bus interface
•
Translates between GTL/GTL+ logic levels (B ports) and
LVTTL/TTL logic levels (A ports)
DESCRIPTION
The GTL16612 is a high-performance BiCMOS product designed for
V
CC
operation at 3.3 V with I/O compatibility up to 5 V.
This device is an 18-bit universal transceiver featuring non-inverting
3-State bus compatible outputs in both send and receive directions.
Data flow in each direction is controlled by output enable (OEAB and
OEBA), latch enable (LEAB and LEBA), and clock (CPAB and
CPBA) inputs. For A-to-B data flow, the device operates in the
transparent mode when LEAB is High. When LEAB is Low, the A
data is latched if CPAB is held at a High or Low logic level. If LEAB
is Low, the A-bus data is stored in the latch/flip-flop on the
Low-to-High transition of CPAB. When OEAB is Low, the outputs are
active. When OEAB is High, the outputs are in the high-impedance
state. The clocks can be controlled with the clock-enable inputs
(CEBA/CEAB).
Data flow for B-to-A is similar to that of A-to-B but uses OEBA,
LEBA and CPBA.
•
5 V I/O tolerant on the LVTTL/TTL side (A ports)
•
No bus current loading when LVTTL/TTL output is tied to 5 V bus
•
3-State buffers
•
Output capability: +64 mA/-32 mA on the LVTTL/TTL side
(A ports); +40 mA on the GTL/GTL+ side (B ports)
•
TTL input levels on control pins
•
Power-up reset
•
Power-up 3-State
•
Positive edge triggered clock inputs
•
Latch-up protection exceeds 500 mA per JESD78
•
ESD protection exceeds 2000 V HBM per JESD22-A114,
200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101
QUICK REFERENCE DATA
SYMBOL
t
PLH
t
PHL
C
IN
C
I/O
I
CCZ
PARAMETER
Propagation delay
An to Bn or Bn to An
Input capacitance (Control pins)
I/O pin capacitance
Total supply current
C
L
= 50 pF
V
I
= 0 V or V
CC
Outputs disabled; V
I/O
= 0 V or V
CC
Outputs disabled
CONDITIONS
T
amb
= 25
°C
TYPICAL
UNIT
3.3 V
1.9
4
8
12
ns
pF
pF
mA
ORDERING INFORMATION
PACKAGES
56-Pin Plastic SSOP
56-Pin Plastic TSSOP
TEMPERATURE RANGE
-40 to +85
°C
-40 to +85
°C
ORDER CODE
GTL16612DL
GTL16612DGG
DWG NUMBER
SOT371-1
SOT364-1
Standard packing quantities and other packaging data is available at www.philipslogic.com/packaging.
2002 Dec 13
2
Philips Semiconductors
Product specification
18-bit GTL/GTL
+
to LVTTL/TTL bidirectional
universal translator (3-State)
GTL16612
PIN CONFIGURATION
OEAB
LEAB
A0
GND
A1
A2
V
CC
A3
A4
A5
GND
A6
A7
A8
A9
A10
A11
GND
A12
A13
A14
V
CC
A15
A16
GND
A17
OEBA
LEBA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
SW00485
CEAB
CPAB
B0
GND
B1
B2
NC
B3
B4
B5
GND
B6
B7
B8
B9
B10
B11
GND
B12
B13
B14
V
REF
B15
B16
GND
B17
CPBA
CEBA
PIN DESCRIPTION
PIN NUMBER
1, 27
29, 56
2, 28
55,30
3, 5, 6, 8, 9, 10,
12, 13, 14, 15,
16, 17, 19, 20,
21, 23, 24, 26
54, 52, 51, 49,
48, 47, 45, 44,
43, 42, 41, 40,
38, 37, 36, 34,
33, 31
4, 11, 18, 25,
32, 39, 46, 53
7, 22
35
50
SYMBOL
OEAB/OEBA
CEBA/CEAB
LEAB/LEBA
CPAB/CPBA
NAME AND FUNCTION
A-to-B/ B-to-A Output enable
input (active Low)
B-to-A/A-to-B clock enable
A-to-B/B-to-A Latch enable input
A-to-B/B-to-A Clock input
(active rising edge)
A0-A17
Data inputs/outputs (A side)
B0-B17
Data inputs/outputs (B side)
GND
V
CC
V
REF
NC
Ground (0 V)
Positive supply voltage
GTL reference voltage
No connection
2002 Dec 13
3
Philips Semiconductors
Product specification
18-bit GTL/GTL
+
to LVTTL/TTL bidirectional
universal translator (3-State)
GTL16612
LOGIC SYMBOL (Positive Logic)
OEAB
1
CEAB
56
CPAB
55
LEAB
2
LEBA
28
CPBA
30
CEBA
29
OEBA
27
CE
A0
3
1D
C1
CLK
CE
1D
C1
CLK
54
B0
To 17 other channels
SW00254
FUNCTION TABLE
INPUTS
CEAB
1
X
X
X
H
H
L
L
L
L
OEAB
1
H
L
L
L
L
L
L
L
L
LEAB
1
X
H
H
L
L
L
L
L
L
CPAB
1
X
X
X
X
X
↑
↑
H
L
A
X
L
H
X
X
L
H
X
X
OUTPUT
B
Z
L
H
B
O
2
B
O2
L
H
B
O2
B
O3
X = Don’t care
H = High voltage level
L = Low voltage level
↑
= Low to High
Z = High impedance “off” state
1. A-to-B data flow is shown: B-to-A flow is similar but uses OEBA, LEBA, CPBA, and CEBA.
2. Output level before the indicated steady-state input conditions were established.
3. Output level before the indicated steady-state input conditions were established, provided that CPAB was Low before LEAB went Low.
2002 Dec 13
4
Philips Semiconductors
Product specification
18-bit GTL/GTL
+
to LVTTL/TTL bidirectional
universal translator (3-State)
GTL16612
ABSOLUTE MAXIMUM RATINGS
1, 2
SYMBOL
V
CC
I
IK
V
I
I
OK
V
O
PARAMETER
DC supply voltage
DC input diode current
DC input voltage
3
DC output diode current
DC output voltage
3
V
I
< 0
A port
B port
V
O
< 0; A port
Output in Off or High state; A port
Output in Off or High state; B port
A port
I
OL
I
OH
T
stg
Current into any output in the LOW state
B port
Current into any output in the HIGH state
Storage temperature range
A port
80
-64
-65 to +150
mA
mA
°C
CONDITIONS
RATING
-0.5 to +4.6
-50
-0.5 to +7.0
V
-0.5 to +4.6
-50
-0.5 to +7.0
-0.5 to +4.6
128
mA
V
V
mA
UNIT
V
mA
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
3.3 V RANGE LIMITS
SYMBOL
V
CC
V
TT
PARAMETER
DC supply voltage
GTL
Termination voltage
GTL
+
GTL
V
REF
GTL reference voltage
GTL
+
B port
V
I
Input voltage
Except B port
B port
V
IH
HIGH-level input voltage
Except B port
B port
V
IL
I
OH
I
OL
T
amb
LOW-level input voltage
Except A port
HIGH-level output current
LOW-level output current
A port
Operating free-air temperature range
-40
64
+85
°C
A port
B port
0
V
REF
+50 mV
2.0
V
REF
-50 mV
0.8
-32
40
mA
mA
V
TEST CONDITIONS
MIN
3.0
1.14
1.35
0.74
0.9
0
MAX
3.6
1.26
V
1.65
0.87
V
1.10
V
TT
5.5
V
V
V
UNIT
2002 Dec 13
5
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