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74AHC377; 74AHCT377
Octal D-type flip-flop with data enable; positive-edge trigger
Rev. 02 — 12 June 2008
Product data sheet
1. General description
The 74AHC377; 74AHCT377 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard
No. 7-A.
The 74AHC377; 74AHCT377 has eight edge-triggered, D-type flip-flops with individual D
inputs and Q outputs. A common clock input (CP) loads all flip-flops simultaneously when
the data enable input (E) is LOW. The state of each D input, one set-up time before the
LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the
flip-flop. The E input is only required to be stable one set-up time prior to the
LOW-to-HIGH transition for predictable operation.
For versions associated with the 74AHC377; 74AHCT377, refer to the following:
•
For the master reset version, see 74AHC273; 74AHCT273
•
For the transparent latch version, see 74AHC373; 74AHCT373
•
For the 3-state version, see 74AHC374; 74AHCT374
2. Features
I
I
I
I
I
I
I
Balanced propagation delays
All inputs have Schmitt-trigger actions
Inputs accept voltages higher than V
CC
Ideal for addressable register applications
Data enable for address and data synchronization
Eight positive-edge triggered D-type flip-flops
Input levels:
N
For 74AHC377: CMOS level
N
For 74AHCT377: TTL level
I
ESD protection:
N
HBM EIA/JESD22-A114E exceeds 2000 V
N
MM EIA/JESD22-A115-A exceeds 200 V
N
CDM EIA/JESD22-C101C exceeds 1000 V
I
Multiple package options
I
Specified from
−40 °C
to +85
°C
and from
−40 °C
to +125
°C
NXP Semiconductors
74AHC377; 74AHCT377
Octal D-type flip-flop with data enable; positive-edge trigger
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74AHC377
74AHC377D
74AHC377PW
74AHCT377
74AHCT377D
74AHCT377PW
−40 °C
to +125
°C
−40 °C
to +125
°C
SO20
TSSOP20
plastic small outline package; 20 leads;
body width 7.5 mm
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
SOT163-1
SOT360-1
−40 °C
to +125
°C
−40 °C
to +125
°C
SO20
TSSOP20
plastic small outline package; 20 leads;
body width 7.5 mm
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
SOT163-1
SOT360-1
Description
Version
Type number
4. Functional diagram
3
4
7
8
D0
Q0
Q1
Q2
FF1
to
FF8
2
5
6
9
D1
D2
D3
OUTPUTS
Q3
13
D4
14
D5
17
D6
18
D7
Q4
12
Q5
15
Q6
16
Q7
19
1
E
11 CP
mna606
Fig 1.
Functional diagram
74AHC_AHCT377_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 12 June 2008
2 of 16
NXP Semiconductors
74AHC377; 74AHCT377
Octal D-type flip-flop with data enable; positive-edge trigger
11
1
11
3
4
7
8
13
14
17
18
CP
D0
D1
D2
D3
D4
D5
D6
D7
E
1
mna918
1C2
G1
3
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2
5
6
9
12
15
16
19
17
18
4
7
8
13
14
2D
2
5
6
9
12
15
16
19
mna919
Fig 2.
Logic symbol
Fig 3.
IEC logic symbol
D0
D1
D2
D3
D4
D5
D6
D7
E
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
FF1
CP
FF2
FF3
FF4
FF5
FF6
FF7
FF8
Q0
Q1
Q2
Q3
Q4
Q5
Q6
mna610
Q7
Fig 4.
Logic diagram
74AHC_AHCT377_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 12 June 2008
3 of 16
NXP Semiconductors
74AHC377; 74AHCT377
Octal D-type flip-flop with data enable; positive-edge trigger
5. Pinning information
5.1 Pinning
E
Q0
D0
D1
Q1
Q2
D2
D3
Q3
1
2
3
4
5
6
7
8
9
20 V
CC
19 Q7
18 D7
17 D6
377
16 Q6
15 Q5
14 D5
13 D4
12 Q4
11 CP
mna917
GND 10
Fig 5.
Pin configuration SO20 and TSSOP20
5.2 Pin description
Table 2.
Symbol
E
Q0
D0
D1
Q1
Q2
D2
D3
Q3
GND
CP
Q4
D4
D5
Q5
Q6
D6
D7
Q7
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Description
data enable input (active LOW)
flip-flop output
data input
data input
flip-flop output
flip-flop output
data input
data input
flip-flop output
ground (0 V)
clock input (LOW-to-HIGH, edge triggered)
flip-flop output
data input
data input
flip-flop output
flip-flop output
data input
data input
flip-flop output
supply voltage
74AHC_AHCT377_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 12 June 2008
4 of 16
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