74ACT574
OCTAL D-TYPE FLIP-FLOP
WITH 3 STATE OUTPUTS (NON INVERTED)
s
s
s
s
s
s
s
s
s
HIGH SPEED:
f
MAX
= 270MHz (TYP.) at V
CC
= 5.0V
LOW POWER DISSIPATION:
I
CC
= 4µA(MAX.) at T
A
=25°C
COMPATIBLE WITH TTL OUTPUTS
V
IH
= 2V (MIN.), V
IL
= 0.8V (MAX.)
50Ω TRANSMISSION LINE DRIVING
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 24mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
≅
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 4.5V to 5.5V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 574
IMPROVED LATCH-UP IMMUNITY
DIP
SOP
TSSOP
ORDER CODES
PACKAGE
DIP
SOP
TSSOP
TUBE
74ACT574B
74ACT574M
DESCRIPTION
The 74ACT574 is an advanced high-speed CMOS
OCTAL D-TYPE FLIP-FLOP with 3 STATE
OUTPUT NON INVERTING fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS technology.
These 8 bit D-Type Flip-Flop are controlled by a
clock input (CK) and an output enable input (OE).
On the positive transition of the clock, the Q
outputs will be set to the logic that were setup at
the D inputs.
While the (OE) input is low, the 8 outputs will be in
PIN CONNECTION AND IEC LOGIC SYMBOLS
O
so
b
te
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ro
P
uc
d
s)
t(
so
b
-O
a normal logic state (high or low logic level) and
while high level the outputs will be in a high
impedance state.
The output control does not affect the internal
operation of flip-flops; that is, the old data can be
retained or the new data can be entered even
while the outputs are off.
This device is designed to interface directly High
Speed CMOS systems with TTL and NMOS
components.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
P
te
le
od
r
s)
t(
uc
T&R
74ACT574MTR
74ACT574TTR
April 2001
1/11
74ACT574
AC ELECTRICAL CHARACTERISTICS
(C
L
= 50 pF, R
L
= 500
Ω,
Input t
r
= t
f
= 3ns)
Test Condition
Symbol
Parameter
V
CC
(V)
5.0
(*)
5.0
(*)
5.0
(*)
5.0
(*)
5.0
(*)
5.0
(*)
5.0
(*)
100
T
A
= 25°C
Min.
Typ.
5.0
5.5
5.0
1.5
1.0
-1.0
270
Max.
10.0
9.0
8.5
3..0
2.5
2.5
85
Value
-40 to 85°C
Min.
Max.
11.0
10.0
9.0
4.0
3.0
3.0
-55 to 125°C
Min.
Max.
11.0
10.0
9.0
4.0
3.0
3.0
ns
ns
ns
ns
ns
ns
Unit
t
PLH
t
PHL
Propagation Delay
Time CK to Q
t
PZL
t
PZH
Output Enable
Time
t
PLZ
t
PHZ
Output Disable
Time
t
W
CK Pulse Width
HIGH or LOW
t
s
Setup Time D to
CK, HIGH or LOW
t
h
Hold Time D to CK,
HIGH or LOW
f
MAX
Maximum CK
Frequency
(*) Voltage range is 5.0V
±
0.5V
CAPACITIVE CHARACTERISTICS
Test Condition
Symbol
Parameter
V
CC
(V)
5.0
5.0
5.0
T
A
= 25°C
Min.
C
IN
C
OUT
C
PD
Input Capacitance
Output
Capacitance
Power Dissipation
Capacitance (note
1)
1) C
PD
is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
/n (per circuit)
O
so
b
te
le
ro
P
uc
d
s)
t(
b
-O
so
4
8
26
Typ.
P
te
le
Value
Max.
Min.
od
r
Max.
s)
t(
uc
85
Max.
MHz
-40 to 85°C
-55 to 125°C
Min.
Unit
pF
pF
pF
f
IN
= 10MHz
5/11
嵌入式系统
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