The CY7C1059DV33 is a high performance CMOS Static RAM
organized as 1M words by 8 bits. Easy memory expansion is
provided by an active LOW Chip Enable (CE), an active LOW
Output Enable (OE), and tri-state drivers. To write to the device,
take Chip Enable (CE) and Write Enable (WE) inputs LOW. Data
on the eight I/O pins (I/O
0
through I/O
7
) is then written into the
location specified on the address pins (A
0
through A
19
).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under
these conditions, the contents of the memory location specified
by the address pins appear on the I/O pins.
The eight input or output pins (I/O
0
through I/O
7
) are placed in a
high impedance state when the device is deselected (CE HIGH),
the outputs are disabled (OE HIGH), or a write operation is in
progress (CE LOW and WE LOW).
The CY7C1059DV33 is available in 44-pin TSOP-II package with
center power and ground (revolutionary) pinout.
For a complete list of related documentation, click
here.
High speed
❐
t
AA
= 10 ns
Low active power
❐
I
CC
= 110 mA at f = 100 MHz
Low CMOS standby power
❐
I
SB2
= 20 mA
2.0 V data retention
Automatic power down when deselected
TTL-compatible inputs and outputs
Easy memory expansion with CE and OE features
Available in Pb-free 44-pin TSOP-II package
Offered in standard and high reliability (Q) grades
■
■
■
■
■
■
■
■
Logic Block Diagram
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
CE
WE
OE
INPUT BUFFER
ROW DECODER
IO0
IO1
SENSE AMPS
IO2
IO3
IO4
IO5
IO6
1M x 8
ARRAY
COLUMN DECODER
POWER
DOWN
IO7
A11
A12
A13
A14
A15
A16
A17
A18
A19
Cypress Semiconductor Corporation
Document Number: 001-00061 Rev. *J
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised January 16, 2015
CY7C1059DV33
Pin Configuration
Figure 1. 44-Pin TSOP II
Top View
NC
NC
A
0
A
1
A
2
A
3
A
4
CE
I/O
0
I/O
1
V
CC
V
SS
I/O
2
I/O
3
WE
A
5
A
6
A
7
A
8
A
9
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
NC
NC
A
18
A
17
A
16
A
15
OE
I/O
7
I/O
6
V
SS
V
CC
I/O
5
I/O
4
A
14
A
13
A
12
A
11
A
10
A
19
NC
NC
Selection Guide
Description
Maximum access time
Maximum operating current
Maximum CMOS standby current
–10
10
110
20
–12
12
100
20
Unit
ns
mA
mA
Document Number: 001-00061 Rev. *J
Page 2 of 11
CY7C1059DV33
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature ................................ –65
C
to +150
C
Ambient temperature with
power applied ........................................... –55
C
to +125
C
Supply voltage on V
CC
to relative GND
[1]
....–0.5 V to + 4.6 V
DC voltage applied to outputs
in high-Z state
[1]
................................... –0.3 V to V
CC
+ 0.3 V
DC input voltage
[1]
............................... –0.3 V to V
CC
+ 0.3 V
Current into outputs (LOW) ......................................... 20 mA
Static discharge voltage............. ...............................>2001 V
(MIL-STD-883, Method 3015)
Latch-up current ...................................................... >200 mA
Operating Range
Range
Industrial
Ambient Temperature
–40
C
to +85
C
V
CC
3.3 V
0.3 V
Electrical Characteristics
Over the Operating Range
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
I
SB2
Description
Output HIGH voltage
Output LOW voltage
Input HIGH voltage
Input LOW voltage
[1]
Input leakage current
Output leakage current
V
CC
operating
supply current
Automatic CE power-down
current — TTL inputs
Automatic CE power-down
current — CMOS inputs
GND < V
IN
< V
CC
GND < V
OUT
< V
CC
, output disabled
V
CC
= Max., f = f
MAX
= 1/t
RC
Max. V
CC
, CE > V
IH,
V
IN
> V
IH
or V
IN
< V
IL
, f = f
MAX
Max. V
CC
, CE > V
CC
– 0.3 V,
V
IN
> V
CC
– 0.3 V, or V
IN
< 0.3 V, f = 0
Test Conditions
V
CC
= Min, I
OH
= –4.0 mA
V
CC
= Min I
OL
= 8.0 mA
–10
Min
2.4
–
2.0
–0.3
–1
–1
–
–
–
Max
–
0.4
V
CC
+ 0.3
0.8
+1
+1
110
40
20
Min
2.4
–
2.0
–0.3
–1
–1
–
–
–
–12
Max
–
0.4
V
CC
+ 0.3
0.8
+1
+1
100
35
20
Unit
V
V
V
V
A
A
mA
mA
mA
Capacitance
Tested initially and after any design or process changes that may affect these parameters
.
Parameter
C
IN
C
OUT
Description
Input capacitance
I/O capacitance
Test Conditions
T
A
= 25
C,
f = 1 MHz,
V
CC
= 3.3 V
Max
12
12
Unit
pF
pF
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
JA
JC
Description
Thermal resistance
(Junction to ambient)
Thermal resistance
(Junction to case)
Test Conditions
Still air, soldered on a 3 × 4.5 inch, four-layer printed
circuit board
TSOP II
51.43
15.8
Unit
C/W
C/W
Notes
1. V
IL(min)
= –2.0 V and V
IH(max)
= V
CC
+ 2 V for pulse durations of less than 20 ns.
2. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 001-00061 Rev. *J
Page 3 of 11
CY7C1059DV33
AC Test Loads and Waveforms
AC characteristics (except High-Z) are tested using the load conditions shown in
Figure 2
(a). High-Z characteristics are tested for all
speeds using the test load shown in
Figure 2
(c).
Figure 2. AC Test Loads and Waveforms
Z = 50
OUTPUT
50
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
3.0 V
30 pF*
GND
ALL INPUT PULSES
90%
10%
90%
10%
1.5 V
(a)
Rise Time: 1 V/ns
R 317
(b)
Fall Time: 1 V/ns
High-Z characteristics:
3.3 V
OUTPUT
5 pF
(c)
R2
351
Data Retention Characteristics
Over the Operating Range
Parameter
V
DR
I
CCDR
t
CDR[2]
t
R[4]
Description
V
CC
for data retention
Data retention current
Chip deselect to data
retention time
Operation recovery time
Figure 3. Data Retention Waveform
DATA RETENTION MODE
V
CC
CE
3.0 V
t
CDR
V
DR
>
2 V
3.0 V
t
R
Conditions
[3]
V
CC
= V
DR
= 2.0 V, CE > V
CC
– 0.3 V,
V
IN
> V
CC
– 0.3 V or V
IN
< 0.3 V
Min
2.0
–
0
t
RC
Max
–
20
–
–
Unit
V
mA
ns
ns
Notes
3. No inputs may exceed V
CC
+ 0.3 V.
4. Full device operation requires linear V
CC
ramp from V
DR
to V
CC(min)
> 50
s
or stable at V
CC(min)
> 50
s.
Document Number: 001-00061 Rev. *J
Page 4 of 11
CY7C1059DV33
AC Switching Characteristics
Over the Operating Range
[5]
Parameter
Read Cycle
t
power[6]
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
V
CC
(typical) to the first access
Read cycle time
Address to data valid
Data hold from address change
CE LOW to data valid
OE LOW to data valid
OE LOW to low-Z
OE HIGH to high-Z
[7, 8]
CE LOW to low-Z
[8]
CE HIGH to high-Z
[7, 8]
CE LOW to power-up
CE HIGH to power-down
Write cycle time
CE LOW to write end
Address setup to write end
Address hold from write end
Address setup to write start
WE pulse width
Data setup to write end
Data hold from write end
WE HIGH to low-Z
[8]
WE LOW to high-Z
[7, 8]
100
10
–
2.5
–
–
0
–
3
–
0
–
10
7
7
0
0
7
5
0
3
–
–
–
10
–
10
5
–
5
–
5
–
10
–
–
–
–
–
–
–
–
–
5
100
12
–
2.5
–
–
0
–
3
–
0
–
12
8
8
0
0
8
6
0
3
–
–
–
12
–
12
6
–
6
–
6
–
12
–
–
–
–
–
–
–
–
–
6
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
–10
Min
Max
Min
–12
Max
Unit
Write Cycle
[9, 10]
Notes
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V.
6. t
POWER
is the minimum amount of time that the power supply must be at stable, typical V
CC
values until the first memory access can be performed.
7. t
HZOE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in part (d) of
“AC Test Loads and Waveforms” on page 4.
Transition is measured when
the outputs enter a high impedance state.
8. At any temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any device.
9. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either
of these signals can terminate the write. The input data setup and hold timing must refer to the leading edge of the signal that terminates the Write.
10. The minimum write cycle time for Write Cycle No. 2 (WE controlled, OE LOW) is the sum of t
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