MB9B520M Series
32-bit ARM
®
Cortex
®
-M3
FM3 Microcontroller
The MB9B520M Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers with low-power
consumption mode and competitive cost.
These series are based on the ARM Cortex -M3 Processor with on-chip Flash memory and SRAM, and have peripheral functions
2
such as various timers, ADCs, DACs and Communication Interfaces (USB, CAN, UART, CSIO, I C, LIN).
The products which are described in this data sheet are placed into TYPE9 product categories in “FM3 Family Peripheral Manual”.
®
®
Features
32-bit ARM Cortex -M3 Core
Processor version: r2p1
Up to 72 MHz Frequency Operation
Integrated Nested Vectored Interrupt Controller (NVIC): 1
NMI (non-maskable interrupt) and 48 peripheral interrupts
and 16 priority levels
®
®
[USB device]
USB2.0 Full-Speed supported
Max 6 EndPoint supported
0 is control transfer
EndPoint 1, 2 can select Bulk-transfer, Interrupt-transfer or
Isochronous-transfer
EndPoint 3 to 5 can select Bulk-transfer or
Interrupt-transfer
EndPoint 1 to 5 are comprised of Double Buffers.
The size of each endpoint is according to the follows.
• Endpoint 0, 2 to 5 : 64 bytes
• Endpoint 1 : 256 bytes
EndPoint
24-bit System timer (Sys Tick): System timer for OS task
management
On-chip Memories
[Flash memory]
Dual operation Flash memory
Operation Flash memory has the upper bank and the
lower bank.
So, this series could implement erase, write and read
operations for each bank simultaneously.
Main area: Up to 256 Kbytes (Up to 240 Kbytes upper bank
+ 16 Kbytes lower bank)
Work area: 32 Kbytes (lower bank)
Dual
[USB host]
USB2.0 Full/Low-speed supported
Bulk-transfer, interrupt-transfer and Isochronous-transfer
support
USB Device connected/dis-connected automatic detection
Automatic processing of the IN/OUT token handshake
packet
Read cycle: 0 wait-cycle
Security function for code protection
[SRAM]
This Series on-chip SRAM is composed of two independent
SRAM (SRAM0, SRAM1). SRAM0 is connected to I-code bus
and D-code bus of Cortex-M3 core. SRAM1 is connected to
System bus.
Max 256-byte packet-length supported
Wake-up function supported
CAN Interface
Compatible with CAN Specification 2.0A/B
Maximum transfer rate: 1 Mbps
Built-in 32 message buffer
Multi-function Serial Interface (Max eight channels)
SRAM0: Up to 16 Kbytes
SRAM1: Up to 16 Kbytes
USB Interface
The USB interface is composed of Device and Host.
PLL for USB is built-in, USB clock can be generated by
multiplication of Main clock.
4 channels with 16 steps×9-bit FIFO (ch.0/1/3/4), 4 channels
without FIFO (ch.2/5/6/7)
Operation mode is selectable from the followings for each
channel.
UART
CSIO
LIN
2
I C
Cypress Semiconductor Corporation
Document Number: 002-05649 Rev.*C
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised June 15, 2017
MB9B520M Series
[UART]
Full duplex double buffer
Selection with or without parity supported
Built-in dedicated baud rate generator
External clock available as a serial clock
Hardware Flow control: Automatically control the
transmission/reception by CTS/RTS (only ch.4)
A/D Converter (Max 26 channels)
[12-bit A/D Converter]
Successive Approximation type
Built-in 2 units
Conversion time: 0.8 μs @ 5 V
Priority conversion available (priority at 2 levels)
Scanning conversion mode
Built-in FIFO for conversion data storage (for SCAN
conversion: 16 steps, for Priority conversion:
4 steps)
Various error detection functions available (parity errors,
framing errors, and overrun errors)
[CSIO]
Full duplex double buffer
Built-in dedicated baud rate generator
Overrun error detection function available
[LIN]
LIN protocol Rev.2.1 supported
Full duplex double buffer
Master/Slave mode supported
LIN break field generation (can be changed to 13 to 16-bit
length)
D/A Converter (Max two channels)
R-2R type
10-bit resolution
Base Timer (Max eight channels)
Operation mode is selectable from the followings for each
channel.
16-bit PWM timer
16-bit PPG timer
16-/32-bit reload timer
16-/32-bit PWC timer
General-Purpose I/O Port
This series can use its pins as general-purpose I/O ports when
they are not used for peripherals. Moreover, the port relocate
function is built in. It can set which I/O port the peripheral
function can be allocated to.
LIN break delimiter generation (can be changed to 1 to 4-bit
length)
Various error detection functions available (parity errors,
framing errors, and overrun errors)
[I C]
Standard mode (Max 100 kbps) / Fast mode (Max 400 kbps)
supported
2
DMA Controller (Eight channels)
The DMA Controller has an independent bus from the CPU, so
CPU and DMA Controller can process simultaneously.
Capable of pull-up control per pin
Capable of reading pin level directly
Built-in the port relocate function
Up to 65 high-speed general-purpose I/O Ports@80pin
Package
8 independently configured and operated channels
Transfer can be started by software or request from the
built-in peripherals
Some ports are 5V tolerant.
See “List of Pin Functions” and “I/O Circuit Type” to confirm
the corresponding pins.
Transfer address area: 32-bit (4 Gbytes)
Transfer mode: Block transfer/Burst transfer/Demand
transfer
Transfer data type: byte/half-word/word
Transfer block count: 1 to 16
Number of transfers: 1 to 65536
Dual Timer (32-/16-bit Down Counter)
The Dual Timer consists of two programmable 32-/16-bit down
counters.
Operation mode is selectable from the followings for each
channel.
Free-running
Periodic (=Reload)
One-shot
Document Number: 002-05649 Rev.*C
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MB9B520M Series
Quadrature Position/Revolution Counter (QPRC)
(Max two channels)
The Quadrature Position/Revolution Counter (QPRC) is used
to measure the position of the position encoder. Moreover, it is
possible to use as the up/down counter.
External Interrupt Controller Unit
Up to 23 external interrupt input pins @ 80 pin Package
Include one non-maskable interrupt (NMI) input pin
Watchdog Timer (Two channels)
A watchdog timer can generate interrupts or a reset when a
time-out value is reached.
This series consists of two different watchdogs, a "Hardware"
watchdog and a "Software" watchdog.
The "Hardware" watchdog timer is clocked by the built-in
Low-speed CR oscillator. Therefore, the "Hardware" watchdog
is active in any low-power consumption modes except RTC,
Stop, Deep Standby RTC, Deep Standby Stop modes.
The detection edge of the three external event input pins AIN,
BIN and ZIN is configurable.
16-bit position counter
16-bit revolution counter
Two 16-bit compare registers
Multi-function Timer
The Multi-function timer is composed of the following blocks.
16-bit free-run timer × 3 ch./unit
Input capture × 4 ch./unit
Output compare × 6 ch./unit
A/D activation compare × 2 ch./unit
Waveform generator × 3 ch./unit
16-bit PPG timer × 3 ch./unit
The following function can be used to achieve the motor
control.
CRC (Cyclic Redundancy Check) Accelerator
The CRC accelerator calculates the CRC which has a heavy
software processing load, and achieves a reduction of the
integrity check processing load for reception data and storage.
CCITT CRC16 and IEEE-802.3 CRC32 are supported.
CCITT CRC16 Generator Polynomial: 0x1021
IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7
Clock and Reset
[Clocks]
Selectable from five clock sources (2 external oscillators, 2
built-in CR oscillators, and Main PLL).
PWM signal output function
DC chopper waveform output function
Dead time function
Input capture function
A/D convertor activate function
DTIF (Motor emergency stop) interrupt function
Real-time clock (RTC)
The Real-time clock can count
Year/Month/Day/Hour/Minute/Second/A day of the week from
00 to 99.
Main Clock:
Sub Clock:
4 MHz to 48 MHz
32.768 kHz
Built-in High-speed CR Clock: 4 MHz
Built-in Low-speed CR Clock: 100 kHz
Main PLL Clock
[Resets]
Reset requests from INITX pin
Power-on reset
Software reset
Watchdog timers reset
Low-voltage detection reset
Clock Super Visor reset
Clock Super Visor (CSV)
Clocks generated by built-in CR oscillators are used to
supervise abnormality of the external clocks.
The interrupt function with specifying date and time
(Year/Month/Day/Hour/Minute) is available. This function is
also available by specifying only Year, Month, Day, Hour or
Minute.
Timer interrupt function after set time or each set time.
Capable of rewriting the time with continuing the time count.
Leap year automatic count is available.
Watch Counter
The Watch counter is used for wake up from Sleep and Timer
mode.
Interval timer: up to 64 s (Max) @ Sub Clock: 32.768 kHz
If external clock failure (clock stop) is detected, reset is
asserted.
If external frequency anomaly is detected, interrupt or reset is
asserted.
Document Number: 002-05649 Rev.*C
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MB9B520M Series
Low-Voltage Detector (LVD)
This Series includes 2-stage monitoring of voltage on the VCC
pins. When the voltage falls below the voltage that has been
set, Low-Voltage Detector generates an interrupt or reset.
Debug
Serial Wire JTAG Debug Port (SWJ-DP)
Unique ID
Unique value of the device (41 bits) is set.
LVD1: error reporting via interrupt
LVD2: auto-reset operation
Low-Power Consumption Mode
Six low-power consumption modes supported.
Power Supply
Wide range voltage:
VCC
= 2.7 V to 5.5 V
USBVCC = 3.0 V to 3.6 V (when USB is used)
= 2.7 V to 5.5 V (when GPIO is used)
Sleep
Timer
RTC
Stop
Deep Standby RTC (selectable between keeping the value of
RAM and not)
Deep Standby Stop (selectable between keeping the value of
RAM and not)
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MB9B520M Series
Contents
1. Product Lineup .................................................................................................................................................................. 7
2. Packages ........................................................................................................................................................................... 8
3. Pin Assignment ................................................................................................................................................................. 9
4. List of Pin Functions....................................................................................................................................................... 15
5. I/O Circuit Type................................................................................................................................................................ 33
6. Handling Precautions ..................................................................................................................................................... 39
6.1
Precautions for Product Design ................................................................................................................................... 39
6.2
Precautions for Package Mounting .............................................................................................................................. 40
6.3
Precautions for Use Environment ................................................................................................................................ 41
7. Handling Devices ............................................................................................................................................................ 42
8. Block Diagram ................................................................................................................................................................. 44
9. Memory Size .................................................................................................................................................................... 45
10. Memory Map .................................................................................................................................................................... 45
11. Pin Status in Each CPU State ........................................................................................................................................ 48
12. Electrical Characteristics ............................................................................................................................................... 54
12.1 Absolute Maximum Ratings ......................................................................................................................................... 54
12.2 Recommended Operating Conditions.......................................................................................................................... 56
12.3 DC Characteristics....................................................................................................................................................... 57
12.3.1 Current Rating .............................................................................................................................................................. 57
12.3.2 Pin Characteristics ....................................................................................................................................................... 60
12.4 AC Characteristics ....................................................................................................................................................... 61
12.4.1 Main Clock Input Characteristics .................................................................................................................................. 61
12.4.2 Sub Clock Input Characteristics ................................................................................................................................... 62
12.4.3 Built-in CR Oscillation Characteristics .......................................................................................................................... 63
12.4.4 Operating Conditions of Main and USB PLL (In the case of using main clock for input of PLL) ................................... 64
12.4.5 Operating Conditions of Main PLL (In the case of using built-in high-speed CR for input clock of Main PLL).............. 64
12.4.6 Reset Input Characteristics .......................................................................................................................................... 65
12.4.7 Power-on Reset Timing................................................................................................................................................ 65
12.4.8 Base Timer Input Timing .............................................................................................................................................. 66
12.4.9 CSIO/UART Timing ...................................................................................................................................................... 67
12.4.10 External Input Timing ................................................................................................................................................ 75
12.4.11 Quadrature Position/Revolution Counter timing ........................................................................................................ 76
2
12.4.12 I C Timing ................................................................................................................................................................. 78
12.4.13 JTAG Timing ............................................................................................................................................................. 79
12.5 12-bit A/D Converter .................................................................................................................................................... 80
12.5.1 Definition of 12-bit A/D Converter Terms ..................................................................................................................... 82
12.6 10-bit D/A Converter .................................................................................................................................................... 83
12.7 USB Characteristics .................................................................................................................................................... 84
12.8 Low-Voltage Detection Characteristics ........................................................................................................................ 88
12.8.1 Low-Voltage Detection Reset ....................................................................................................................................... 88
12.8.2 Interrupt of Low-Voltage Detection ............................................................................................................................... 89
12.9 Flash Memory Write/Erase Characteristics ................................................................................................................. 90
12.9.1 Write / Erase time......................................................................................................................................................... 90
12.9.2 Write cycles and data hold time ................................................................................................................................... 90
12.10 Return Time from Low-Power Consumption Mode ...................................................................................................... 91
12.10.1 Return Factor: Interrupt/WKUP ................................................................................................................................. 91
Document Number: 002-05649 Rev.*C
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