19-4909; Rev 0; 10/09
Low-Jitter, Wide Frequency Range,
Programmable Clock Generator with 10 Outputs
General Description
The MAX3637 is a highly flexible, precision phase-
locked loop (PLL) clock generator optimized for the next
generation of network equipment that demands low-jitter
clock generation and distribution for robust high-speed
data transmission. The device features subpicosecond
jitter generation, excellent power-supply noise rejection,
and pin-programmable LVDS/LVPECL output interfaces.
The MAX3637 provides nine differential outputs and
one LVCMOS output, divided into three banks. The fre-
quency and output interface of each output bank can be
individually programmed, making this device an ideal
replacement for multiple crystal oscillators and clock dis-
tribution ICs on a system board, saving cost and space.
This 3.3V IC is available in a 7mm x 7mm, 48-pin TQFN
package and operates from -40°C to +85°C.
S
Inputs
TION KIT
EVALUA BLE
AVAILA
EVALUATION KIT AVAILABLE
Features
Crystal Interface: 18MHz to 33.5MHz
LVCMOS Input: 15MHz to 160MHz
Differential Input: 15MHz to 350MHz
Outputs
LVCMOS Output: Up to 160MHz
LVPECL/LVDS Outputs: Up to 800MHz
Three Individual Output Banks
Pin-Programmable Dividers
Pin-Programmable Output Interface
Wide VCO Tuning Range (3.60GHz to 3.83GHz)
Low Phase Jitter
0.34ps
RMS
(12kHz to 20MHz)
0.14ps
RMS
(1.875MHz to 20MHz)
Excellent Power-Supply Noise Rejection
-40NC to +85NC Operating Temperature Range
+3.3V Supply
MAX3637
S
S
S
S
S
S
S
Applications
Ethernet Switch/Router
Wireless Base Station
Fibre Channel SAN
SONET Line Cards
Ordering Information
PART
MAX3637ETM+
TEMP RANGE
-40NC to +85NC
PIN-PACKAGE
48 TQFN-EP*
Typical Application Circuits and Pin Configuration appear at
end of data sheet.
+Denotes
a lead(Pb)-free/RoHS-compliant package.
*EP
= Exposed pad.
Functional Diagram
LVPECL/LVDS
QA0
QA0
MAX3637
LVPECL/LVDS
QA1
QA1
LVPECL/LVDS
XOUT
XO
XIN
LVCMOS
CIN
PLL, DIVIDERS, MUXES
VCO
LVPECL/LVDS
LVPECL/LVDS
QA2
QA2
QA3
QA3
LVPECL/LVDS
QA4
QA4
QB0
QB0
LVPECL/LVDS
DIN
DIN
LVPECL/LVDS
QB1
QB1
QB2
QB2
LVPECL/LVDS
QC
QC
LVCMOS
QCC
1
Low-Jitter, Wide Frequency Range,
Programmable Clock Generator with 10 Outputs
MAX3637
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Range (V
CC
, V
CCA
, V
CCQA
,
V
CCQB
, V
CCQC
, V
CCQCC
) ................................-0.3V to +4.0V
Voltage Range at CIN, IN_SEL, DM, DF[1:0],
DP, PLL_BP, DA[1:0], DB[1:0], DC[1:0],
QA_CTRL1, QA_CTRL2, QB_CTRL,
QC_CTRL, QCC, RES ........................... -0.3V to (V
CC
+ 0.3V)
Voltage Range at DIN,
DIN
........ (V
CC
- 2.35V) to (V
CC
- 0.35V)
Voltage Range at QA[4:0],
QA[4:0],
QB[2:0],
QB[2:0],
QC,
QC
when LVDS Output ... -0.3V to (V
CC
+ 0.3V)
Current into QA[4:0],
QA[4:0],
QB[2:0],
QB[2:0],
QC,
QC
when LVPECL Output ..................................... -56mA
Current into QCC.............................................................
Q50mA
Voltage Range at XIN ...........................................-0.3V to +1.2V
Voltage Range at XOUT .............................-0.3V to (V
CC
- 0.6V)
Continuous Power Dissipation (T
A
= +70NC)
48-Pin TQFN (derate 40mW/NC above +70NC) ..........3200mW
Operating Junction Temperature Range ......... -55NC to +150NC
Storage Temperature Range............................ -65NC to +160NC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
CC
= +3.0V to +3.6V, T
A
= -40°C to +85°C. Typical values are at V
CC
= +3.3V, T
A
= +25°C, unless otherwise noted. Signal applied
to CIN or DIN/DIN only when selected as the reference clock.) (Note 1)
PARAMETER
Supply Current with PLL
Enabled (Note 2)
Supply Current with PLL
Bypassed (Note 2)
SYMBOL
I
CC
CONDITIONS
Configured with LVPECL outputs
Configured with LVDS outputs
Configured with LVPECL outputs
Configured with LVDS outputs
MIN
TYP
170
290
110
230
MAX
215
365
UNITS
mA
mA
LVCMOS/LVTTL CONTROL INPUTS (IN_SEL, DM, DF[1:0], DA[1:0], DB[1:0], DC[1:0], PLL_BP, DP, QA_CTRL1,
QA_CTRL2, QB_CTRL, QC_CTRL)
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Reference Clock Input
Frequency
Input Amplitude Range
Input High Current
Input Low Current
Reference Clock Input Duty-
Cycle Distortion
Input Capacitance
DIFFERENTIAL CLOCK INPUT (DIN,
DIN)
(Note 4)
Differential Input Frequency
f
REF
Input Bias Voltage
Input Differential Voltage Swing
Single-Ended Voltage Range
Input Differential Impedance
Differential Input Capacitance
2
V
CMI
15
V
CC
-
1.8
150
V
CC
-
2.0
80
100
1.5
V
CC
-
1.3
1800
V
CC
-
0.7
120
I
IH
I
IL
V
IH
V
IL
I
IH
I
IL
V
IN
= V
CC
V
IN
= 0V
-80
2.0
0.8
80
V
V
FA
FA
LVCMOS/LVTTL CLOCK INPUT (CIN)
f
REF
Internally AC-coupled (Note 3)
V
IN
= V
CC
V
IN
= 0V
-80
40
1.5
350
60
15
1.2
160
3.6
80
MHz
V
P-P
FA
FA
%
pF
MHz
V
mV
P-P
V
I
pF
Low-Jitter, Wide Frequency Range,
Programmable Clock Generator with 10 Outputs
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= +3.0V to +3.6V, T
A
= -40°C to +85°C. Typical values are at V
CC
= +3.3V, T
A
= +25°C, unless otherwise noted. Signal applied
to CIN or DIN/DIN only when selected as the reference clock.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
800
1.475
0.925
250
400
25
1.125
1.3
25
80
Short together
Short to ground
V
Q__
= V
Q__
= 0V to V
CC
20% to 80%
PLL enabled
PLL bypassed (Note 6)
48
100
3
6
10
160
50
50
800
V
CC
-
1.13
V
CC
-
1.85
0.5
V
O
= 0V to V
CC
20% to 80%, differential load = 100I
PLL enabled
PLL bypassed (Note 6)
48
V
CC
-
0.98
V
CC
-
1.70
0.7
10
140
50
50
160
I
OH
= -12mA
I
OL
= 12mA
20% to 80% (Note 8)
PLL enabled
PLL bypassed (Note 6)
150
42
400
50
50
15
2.6
V
CC
0.4
850
58
240
52
V
CC
-
0.83
V
CC
-
1.55
0.9
240
52
140
UNITS
MHz
V
V
mV
mV
V
mV
I
mA
FA
ps
%
LVDS OUTPUTS (QA[4:0],
QA[4:0],
QB[2:0],
QB[2:0],
QC,
QC)
(Note 5)
Output Frequency
Output High Voltage
Output Low Voltage
Differential Output Voltage
Change in Magnitude
of Differential Output for
Complementary States
Output Offset Voltage
Change in Magnitude of
Output Offset Voltage for
Complementary States
Differential Output Impedance
Output Current
Output Current When Disabled
Output Rise/Fall Time
Output Duty-Cycle Distortion
V
OH
V
OL
|V
OD
|
D|V
OD
|
V
OS
D|V
OS
|
MAX3637
LVPECL OUTPUTS (QA[4:0],
QA[4:0],
QB[2:0],
QB[2:0],
QC,
QC)
(Note 7)
Output Frequency
Output High Voltage
Output Low Voltage
Output-Voltage Swing
(Single-Ended)
Output Current When Disabled
Output Rise/Fall Time
Output Duty-Cycle Distortion
LVCMOS/LVTTL OUTPUT (QCC)
Output Frequency
Output High Voltage
Output Low Voltage
Output Rise/Fall Time
Output Duty-Cycle Distortion
Output Impedance
V
OH
V
OL
MHz
V
V
V
P-P
FA
ps
%
MHz
V
V
ps
%
I
3
Low-Jitter, Wide Frequency Range,
Programmable Clock Generator with 10 Outputs
MAX3637
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= +3.0V to +3.6V, T
A
= -40°C to +85°C. Typical values are at V
CC
= +3.3V, T
A
= +25°C, unless otherwise noted. Signal applied
to CIN or DIN/DIN only when selected as the reference clock.) (Note 1)
PARAMETER
PLL SPECIFICATIONS
VCO Frequency Range
Phase-Frequency Detector
Compare Frequency
PLL Jitter Transfer Bandwidth
25MHz crystal
input (Note 9)
12kHz to 20MHz
1.875MHz to 20MHz
f
VCO
f
PFD
3600
15
130
0.34
0.14
0.34
-56
-45
6
-70
-109
-112
-118
-134
-146
-119
-121
-127
-143
-151
-122
-123
-129
-145
-152
-123
-124
-130
-147
-153
dBc/
Hz
dBc/
Hz
dBc/
Hz
dBc/
Hz
dBc
dBc
ps
P-P
dBc
1.0
ps
RMS
3750
3830
42
MHz
MHz
kHz
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Integrated Phase Jitter
RJ
25MHz LVCMOS or differential input
(Notes 9, 10)
(Note 11)
(Note 11)
LVPECL or LVDS (Note 11)
(Note 12)
f
OFFSET
= 1kHz
f
OFFSET
= 10kHz
Supply-Noise Induced Phase
Spur at LVPECL/LVDS Output
Supply-Noise Induced Phase
Spur at LVCMOS Output
Determinisitic Jitter Induced by
Power-Supply Noise
Nonharmonic and Subharmonic
Spurs
SSB Phase Noise at 622.08MHz
f
OFFSET
= 100kHz
f
OFFSET
= 1MHz
f
OFFSET
R
10MHz
f
OFFSET
= 1kHz
f
OFFSET
= 10kHz
SSB Phase Noise at 212.5MHz
f
OFFSET
= 100kHz
f
OFFSET
= 1MHz
f
OFFSET
R
10MHz
f
OFFSET
= 1kHz
f
OFFSET
= 10kHz
SSB Phase Noise at 156.25MHz
f
OFFSET
= 100kHz
f
OFFSET
= 1MHz
f
OFFSET
R
10MHz
f
OFFSET
= 1kHz
f
OFFSET
= 10kHz
SSB Phase Noise at 125MHz
f
OFFSET
= 100kHz
f
OFFSET
= 1MHz
f
OFFSET
R
10MHz
4
Low-Jitter, Wide Frequency Range,
Programmable Clock Generator with 10 Outputs
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= +3.0V to +3.6V, T
A
= -40°C to +85°C. Typical values are at V
CC
= +3.3V, T
A
= +25°C, unless otherwise noted. Signal applied
to CIN or DIN/DIN only when selected as the reference clock.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
f
OFFSET
= 1kHz
f
OFFSET
= 10kHz
SSB Phase Noise at 62.5MHz
f
OFFSET
= 100kHz
f
OFFSET
= 1MHz
f
OFFSET
R
10MHz
MIN
TYP
-129
-130
-137
-152
-156
dBc/
Hz
MAX
UNITS
MAX3637
Note 1:
A series resistor of up to 10.5I is allowed between V
CC
and V
CCA
for filtering supply noise when system power-supply
tolerance is V
CC
= 3.3V
Q5%.
See Figure 3.
Note 2:
Measured with all outputs enabled and unloaded.
Note 3:
CIN can be AC- or DC-coupled. See Figure 8. Input high voltage must be ≤ V
CC
+ 0.3V.
Note 4:
DIN can be AC- or DC-coupled. See Figure 10.
Note 5:
Measured with 100I differential load.
Note 6:
Measured with crystal input, or with 50% duty cycle LVCMOS or differential input.
Note 7:
Measured with output termination of 50I to V
CC
- 2V or Thevenin equivalent.
Note 8:
Measured with a series resistor of 33I to a load capacitance of 3.0pF. See Figure 1.
Note 9:
Measured at 156.25MHz output.
Note 10:
Measured using LVCMOS/LVTTL input with slew rate
R
1.0V/ns, or differential input with slew rate
R
0.5V/ns.
Note 11:
Measured at 156.25MHz output with 200kHz, 50mV
P-P
sinusoidal signal on the supply using the crystal input and
the power-supply filter shown in Figure 3. See the
Typical Operating Characteristics
for other supply noise frequen-
cies. Deterministic jitter is calculated from the measured power-supply-induced spurs. For more information, refer to
Application Note 4461:
HFAN-04.5.5: Characterizing Power-Supply Noise Rejection in PLL Clock Synthesizers.
Note 12:
Measured with all outputs enabled and all three banks at different frequencies.
LVCMOS
QCC
33
Ω
Z = 50
Ω
3pF
499
Ω
0.1
µ
F
Z = 50
Ω
OSCILLOSCOPE
50
Ω
MAX3637
Figure 1. LVCMOS Output Measurement Setup
5
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