74LVT640
3.3 V Octal transceiver with direction pin; inverting; 3-state
Rev. 3 — 10 April 2017
Product data sheet
1
General description
The 74LVT640 is a high-performance BiCMOS product designed for V
CC
operation
at 3.3 V.
This device is an octal transceiver featuring inverting 3-state bus compatible outputs in
both send and receive directions. The control function implementation minimizes external
timing requirements. The device features an output enable (OE) input for easy cascading
and a direction (DIR) input for direction control.
2
Features and benefits
•
•
•
•
•
•
•
•
•
•
3-state buffers
Octal bidirectional bus interface
Input and output interface capability to systems at 5 V supply
TTL input and output switching levels
Output capability: +64 mA and -32 mA
Bus-hold data inputs eliminate the need for external pull-up resistors for unused inputs
Live insertion/extraction permitted
Power-up 3-state
No bus current loading when output is tied to 5 V bus
Latch-up protection:
–
JESD78: exceeds 500 mA
•
ESD protection:
–
MIL STD 883 method 3015: exceeds 2000 V
–
MM JESD22-A115-A exceeds 200 V
Nexperia
3.3 V Octal transceiver with direction pin; inverting; 3-state
74LVT640
3
Ordering information
Table 1. Ordering information
Type number Package
Temperature
range
74LVT640D
74LVT640DB
74LVT640PW
-40 °C to +85 °C
-40 °C to +85 °C
-40 °C to +85 °C
Name
SO20
SSOP20
TSSOP20
Description
plastic small outline package; 20 leads;
body width 7.5 mm
plastic shrink small outline package; 20 leads;
body width 5.3 mm
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
Version
SOT163-1
SOT339-1
SOT360-1
4
Functional diagram
1
DIR
OE
2
A0
B0
3
A1
B1
4
A2
B2
5
A3
B3
6
A4
B4
7
A5
B5
8
A6
B6
9
A7
B7
11
12
13
14
2
3
4
5
6
7
8
9
19
18
17
16
19
1
G3
3EN1 (BA)
3EN2 (AB)
1
2
15
18
17
16
15
14
13
12
11
aaa-026617
aaa-026616
Figure 1. Logic symbol
Figure 2. IEC logic symbol
74LVT640
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 3 — 10 April 2017
2 / 15
Nexperia
3.3 V Octal transceiver with direction pin; inverting; 3-state
74LVT640
5
Pinning information
5.1 Pinning
74LVT640
DIR
A0
A1
A2
A3
A4
A5
A6
A7
1
2
3
4
5
6
7
8
9
20 V
CC
19 OE
18 B0
17 B1
16 B2
15 B3
14 B4
13 B5
12 B6
11 B7
aaa-026618
74LVT640
DIR
A0
A1
A2
A3
A4
A5
A6
A7
1
2
3
4
5
6
7
8
9
20 V
CC
19 OE
18 B0
17 B1
16 B2
15 B3
14 B4
13 B5
12 B6
11 B7
aaa-026619
GND 10
GND 10
Figure 3. Pin configuration for SO20
Figure 4. Pin configuration for (T)SSOP20
5.2 Pin description
Table 2. Pin description
Symbol
DIR
A0, A1, A2, A3, A4, A5, A6, A7
GND
B0, B1, B2, B3, B4, B5, B6, B7
OE
V
CC
Pin
1
2, 3, 4, 5, 6, 7, 8, 9
10
18, 17, 16, 15, 14, 13, 12, 11
19
20
Description
direction control input
data inputs/outputs
ground (0 V)
data inputs/outputs
output enable input (active LOW)
supply voltage
6
Functional description
[1]
Table 3. Function selection
Inputs
OE
L
L
H
[1]
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
Z = high impedance OFF-state.
Inputs/outputs
DIR
L
H
X
An
Bn
inputs
Z
Bn
inputs
An
Z
74LVT640
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 3 — 10 April 2017
3 / 15
Nexperia
3.3 V Octal transceiver with direction pin; inverting; 3-state
74LVT640
7
Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
CC
V
I
V
O
I
IK
I
OK
I
O
T
stg
T
j
P
tot
[1]
[2]
[3]
Conditions
[1]
Min
-0.5
-0.5
-0.5
-50
-50
-
-64
-65
[2]
Max
+4.6
+7.0
+7.0
-
-
128
-
+150
150
500
Unit
V
V
V
mA
mA
mA
mA
°C
°C
mW
supply voltage
input voltage
output voltage
input clamping current
output clamping current
output current
storage temperature
junction temperature
total power dissipation
T
amb
= -40 °C to +85 °C
[3]
output in OFF or HIGH state
V
I
< 0
V
O
< 0
output in LOW state
output in HIGH state
[1]
-
-
The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which
are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C.
For SO20 packages: above 70 °C derate linearly with 8 mW/K.
For SSOP20 and TSSOP20 packages: above 60 °C derate linearly with 5.5 mW/K.
8
Recommended operating conditions
Conditions
Min
2.7
0
-
-
current duty cycle ≤ 50 %; f
i
≥ 1 kHz
-
-40
-
in free air
outputs enabled
Table 5. Recommended operating conditions
Symbol Parameter
V
CC
V
I
I
OH
I
OL
T
amb
Δt/ΔV
supply voltage
input voltage
HIGH-level output current
LOW-level output current
ambient temperature
input transition rise and fall rate
Max
3.6
5.5
-32
32
64
+85
10
Unit
V
V
mA
mA
mA
°C
ns/V
74LVT640
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 3 — 10 April 2017
4 / 15
Nexperia
3.3 V Octal transceiver with direction pin; inverting; 3-state
74LVT640
9
Static characteristics
Table 6. Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
IK
V
IH
V
IL
V
OH
input clamping voltage
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
Conditions
V
CC
= 2.7 V; I
IK
= -18 mA
-40 °C to +85 °C
Min
-1.2
2.0
-
Unit
-
-
V
V
V
V
V
V
V
V
V
V
V
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
Typ
-
-
[1]
Max
-0.9
0.8
-
-
-
0.2
0.5
0.4
0.5
0.55
10
±1
20
1
-
±100
125
±100
-
-
-
-500
V
CC
= 2.7 V to 3.6 V; I
OH
= -100 μA
V
CC
= 2.7 V; I
OH
= -8 mA
V
CC
= 3.0 V; I
OH
= -32 mA
V
CC
- 0.2 V
CC
- 0.1
2.4
2.0
-
-
-
-
-
-
-
[2]
2.5
2.2
0.1
0.3
0.25
0.3
0.4
1
±0.1
1
0.1
-1
1
60
15
150
-150
-
-
V
OL
LOW-level output voltage
V
CC
= 2.7 V; I
OL
= 100 μA
V
CC
= 2.7 V; I
OL
= 24 mA
V
CC
= 3.0 V; I
OL
= 16 mA
V
CC
= 3.0 V; I
OL
= 32 mA
V
CC
= 3.0 V; I
OL
= 64 mA
I
I
input leakage current
control pins
V
CC
= 0 V or 3.6 V; V
I
= 5.5 V
V
CC
= 3.6 V; V
I
= V
CC
or GND
I/O data pins
V
CC
= 3.6 V; V
I
= 5.5 V
V
CC
= 3.6 V; V
I
= V
CC
V
CC
= 3.6 V; V
I
= 0 V
-
-
-5
-
-
[3]
I
OFF
I
CEX
I
O(pu/pd)
I
BHL
I
BHH
I
BHLO
I
BHHO
I
CC
power-off leakage current
output high leakage
current
power-up/power-down
output current
bus hold LOW current
bus hold HIGH current
bus hold LOW
overdrive current
bus hold HIGH
overdrive current
supply current
V
CC
= 0 V; V
I
or V
O
= 0 V to 4.5 V
output in HIGH-state when V
O
> V
CC
;
V
O
= 5.5 V; V
CC
= 3.0 V
V
CC
≤ 1.2 V; V
O
= 0.5 V to V
CC;
V
I
= GND or V
CC
; OE = don’t care
V
CC
= 3.0 V; V
I
= 0.8 V
V
CC
= 3.0 V; V
I
= 2.0 V
V
CC
= 3.6 V; V
I
= 0 V to 3.6 V
V
CC
= 3.6 V; V
I
= 0 V to 3.6 V
V
CC
= 3.6 V; V
I
= V
CC
or GND; I
O
= 0 A
outputs HIGH
outputs LOW
outputs disabled
-
75
-75
500
-
[4]
-
-
-
0.13
3
0.13
0.19
12
0.19
mA
mA
mA
74LVT640
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 3 — 10 April 2017
5 / 15
NXP MCU
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