MB9A1A0N Series
32-bit ARM
®
Cortex
®
-M3
FM3 Microcontroller
The MB9A1A0N Series are highly integrated 32-bit microcontrollers that dedicated for embedded controllers with low-power
consumption mode and competitive cost.
The MB9A1A0N Series are based on the ARM
®
Cortex
®
-M3 Processor with on-chip Flash memory and SRAM, and have peripheral
functions such as Motor Control Timers, ADCs, DACs and Communication Interfaces (UART, CSIO, I
2
C).
The products which are described in this data sheet are placed into TYPE7 product categories in FM3 Family Peripheral Manual.
Features
32-bit ARM
®
Cortex
®
-M3 Core
Processor version: r2p1
Up to 20 MHz Operation Frequency
Integrated Nested Vectored Interrupt Controller (NVIC): 1
channel NMI (non-maskable interrupt) and
32 channels' peripheral interrupts and 8 priority levels
[CSIO]
Full duplex double buffer
Built-in dedicated baud rate generator
Overrun error detection function available
[I
2
C]
Standard-mode (Max 100 kbps) / Fast-mode (Max 400 kbps)
supported
24-bit System timer (Sys Tick): System timer for OS task
management
On-chip Memories
[Flash memory]
Up to 128 Kbytes
Read cycle: 0 wait-cycle
Security function for code protection
[SRAM]
This series contains a total of up to 16 Kbyte on-chip SRAM
that is connected to System bus of Cortex-M3 core.
A/D Converter (Max 16 channels)
[12-bit A/D Converter]
Successive Approximation type
Conversion time: Min 1.0 μs
Priority conversion available (priority at 2levels)
Scanning conversion mode
Built-in FIFO for conversion data storage (for SCAN
conversion: 16steps, for Priority conversion:
4steps)
D/A Converter (Max 2 channels)
R-2R type
10-bit resolution
Base Timer (Max 8 channels)
Operation mode is selectable from the followings for each
channel.
SRAM1: Up to 16 Kbytes
Multi-function Serial Interface (Max 8 channels)
Operation mode is selectable from the followings for each
channel.
UART
CSIO
I
2
C
[UART]
Full duplex double buffer
Selection with or without parity supported
Built-in dedicated baud rate generator
External clock available as a serial clock
Various error detection functions available (parity errors,
framing errors, and overrun errors)
16-bit PWM timer
16-bit PPG timer
16-/32-bit reload timer
16-/32-bit PWC timer
Cypress Semiconductor Corporation
Document Number: 002-05675 Rev.*C
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised June 12, 2017
MB9A1A0N Series
General-Purpose I/O Port
This series can use its pins as general-purpose I/O ports when
they are not used for peripherals. Moreover, the port relocate
function is built in. It can set which I/O port the peripheral
function can be allocated to.
HDMI-CEC transmitter
Header block automatic transmission by judging Signal free
Generating status interrupt by detecting Arbitration lost
Generating START, EOM, ACK automatically to output CEC
transmission by setting 1 byte data
Capable of pull-up control per pin
Capable of reading pin level directly
Built-in the port relocate function
Up to 84 high-speed general-purpose I/O Ports@100 pin
Package
Generating transmission status interrupt when transmitting 1
block (1 byte data and EOM/ACK)
Real-time clock (RTC)
The Real-time clock can count
Year/Month/Day/Hour/Minute/Second/A day of the week from
00 to 99.
Some ports are 5 V tolerant I/O
See List of Pin Functions and I/O Circuit Type to confirm the
corresponding pins.
The interrupt function with specifying date and time
(Year/Month/Day/Hour/Minute) is available. This function is
also available by specifying only Year, Month, Day, Hour or
Minute.
Multi-function Timer
The Multi-function timer is composed of the following blocks.
16-bit free-run timer × 3ch.
Input capture × 4ch.
Output compare × 6ch.
A/D activation compare × 1ch.
Waveform generator × 3ch.
16-bit PPG timer × 3ch.
IGBT mode is contained
The following function can be used to achieve the motor
control.
Timer interrupt function after set time or each set time.
Capable of rewriting the time with continuing the time count.
Leap year automatic count is available.
External Interrupt Controller Unit
Up to 16 external interrupt input pins
Include one non-maskable interrupt (NMI) input pin
Watchdog Timer (2 channels)
A watchdog timer can generate interrupts or a reset when a
time-out value is reached.
This series consists of two different watchdogs, a Hardware
watchdog and a Software watchdog.
The Hardware watchdog timer is clocked by the built-in
Low-speed CR oscillator. Therefore, the Hardware watchdog is
active in any low-power consumption mode except RTC, Stop,
Deep Standby RTC and Deep Standby Stop modes.
PWM signal output function
DC chopper waveform output function
Dead time function
Input capture function
A/D convertor activate function
DTIF (Motor emergency stop) interrupt function
HDMI-CEC/Remote Control Receiver (Up to 2
channels)
HDMI- CEC receiver / Remote control receiver
Operating modes supporting the following standards can be
selected
SIRCS
NEC/Association for Electric Home Appliances
HDMI-CEC
Clock and Reset
[Clocks]
Selectable from five clock sources (2 external oscillators, 2
built-in CR oscillators, and Main PLL).
Main Clock:
Sub Clock:
4 MHz to 20 MHz
32.768 kHz
Built-in High-speed CR Clock: 4 MHz
Built-in Low-speed CR Clock: 100 kHz
Main PLL Clock
Capable of adjusting detection timings for start bit and data
bit
Equipped with noise filter
Document Number: 002-05675 Rev.*C
Page 2 of 99
MB9A1A0N Series
[Resets]
Reset requests from INITX pin
Power-on reset
Software reset
Watchdog timers reset
Low-voltage detection reset
Clock Super Visor reset
Clock Super Visor (CSV)
Clocks generated by built-in CR oscillators are used to
supervise abnormality of the external clocks.
Low-Power Consumption Mode
Six low-power consumption modes supported.
Sleep
Timer
RTC
Stop
Deep Standby RTC
Deep Standby Stop
The back up register is 16 bytes.
Debug
Serial Wire JTAG Debug Port (SWJ-DP)
If external clock failure (clock stop) is detected, reset is
asserted.
If external frequency anomaly is detected, interrupt or reset is
asserted.
Power Supply
Wide range voltage: VCC = 1.8 V to 5.5 V
Low-Voltage Detector (LVD)
This Series includes 2-stage monitoring of voltage on the VCC.
When the voltage falls below the voltage that has been set,
Low-Voltage Detector generates an interrupt or reset.
LVD1: error reporting via interrupt
LVD2: auto-reset operation
Document Number: 002-05675 Rev.*C
Page 3 of 99
MB9A1A0N Series
Contents
1. Product Lineup .................................................................................................................................................................. 6
2. Packages ........................................................................................................................................................................... 7
3. Pin Assignment ................................................................................................................................................................. 8
4. List of Pin Functions....................................................................................................................................................... 12
5. I/O Circuit Type................................................................................................................................................................ 31
6. Handling Precautions ..................................................................................................................................................... 35
6.1
Precautions for Product Design ................................................................................................................................... 35
6.2
Precautions for Package Mounting .............................................................................................................................. 36
6.3
Precautions for Use Environment ................................................................................................................................ 37
7. Handling Devices ............................................................................................................................................................ 38
8. Block Diagram ................................................................................................................................................................. 40
9. Memory Size .................................................................................................................................................................... 41
10. Memory Map .................................................................................................................................................................... 41
11. Pin Status in Each CPU State ........................................................................................................................................ 44
12. Electrical Characteristics ............................................................................................................................................... 52
12.1 Absolute Maximum Ratings ......................................................................................................................................... 52
12.2 Recommended Operating Conditions.......................................................................................................................... 53
12.3 DC Characteristics....................................................................................................................................................... 54
12.3.1 Current Rating .............................................................................................................................................................. 54
12.3.2 Pin Characteristics ....................................................................................................................................................... 57
12.4 AC Characteristics ....................................................................................................................................................... 58
12.4.1 Main Clock Input Characteristics .................................................................................................................................. 58
12.4.2 Sub Clock Input Characteristics ................................................................................................................................... 59
12.4.3 Built-in CR Oscillation Characteristics .......................................................................................................................... 59
12.4.4 Operating Conditions of Main PLL (In the case of using main clock for input of PLL) .................................................. 60
12.4.5 Operating Conditions of Main PLL (In the case of using the built-in High-speed CR for the input clock
of the Main PLL) ........................................................................................................................................................... 60
12.4.6 Reset Input Characteristics .......................................................................................................................................... 61
12.4.7 Power-on Reset Timing................................................................................................................................................ 61
12.4.8 Base Timer Input Timing .............................................................................................................................................. 62
12.4.9 CSIO/UART Timing ...................................................................................................................................................... 64
12.4.10 External Input Timing ................................................................................................................................................ 72
12.4.11 I
2
C Timing ................................................................................................................................................................. 73
12.4.12 JTAG Timing ............................................................................................................................................................. 74
12.5 12-bit A/D Converter .................................................................................................................................................... 75
12.6 10-bit D/A Converter .................................................................................................................................................... 78
12.7 Low-Voltage Detection Characteristics ........................................................................................................................ 79
12.7.1 Low-Voltage Detection Reset ....................................................................................................................................... 79
12.7.2 Interrupt of Low-Voltage Detection ............................................................................................................................... 80
12.8 Flash Memory Write/Erase Characteristics ................................................................................................................. 82
12.8.1 Write / Erase time......................................................................................................................................................... 82
12.8.2 Write cycles and data hold time ................................................................................................................................... 82
12.9 Return Time from Low-Power Consumption Mode ...................................................................................................... 83
12.9.1 Return Factor: Interrupt/WKUP .................................................................................................................................... 83
12.9.2 Return Factor: Reset .................................................................................................................................................... 85
13. Ordering Information ...................................................................................................................................................... 87
14. Package Dimensions ...................................................................................................................................................... 88
Document Number: 002-05675 Rev.*C
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MB9A1A0N Series
15. Errata................................................................................................................................................................................ 94
15.1 Part Numbers Affected ................................................................................................................................................ 94
15.2 Qualification Status...................................................................................................................................................... 94
15.3 Errata Summary .......................................................................................................................................................... 94
15.4 Errata Detail ................................................................................................................................................................ 94
15.4.1 HDMI-CEC polling message issue ............................................................................................................................... 94
15.4.2 RTC delay issue ........................................................................................................................................................... 95
Major Changes ...................................................................................................................................................................... 96
Document History ................................................................................................................................................................. 98
Sales, Solutions, and Legal Information ............................................................................................................................. 99
Document Number: 002-05675 Rev.*C
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