End of Life. Last Available Purchase Date is 31-Dec-2014
Si9979
Vishay Siliconix
3-Phase Brushless DC Motor Controller
FEATURES
Hall-Effect Commutation
60 or 120 Sensor Spacing
Integral High-Side Drive for all N-Channel MOSFET
Bridges
PWM Input
Quadrature Selection
Tachometer Output
Reversible
Braking
Output Enable Control
Cross Conduction Protection
Current Limiting
Undervoltage Lockout
Internal Pull-Up Resistors
DESCRIPTION
The Si9979 is a monolithic brushless dc motor controller with
integral high-side drive circuitry. The Si9979 is configured to
allow either 60 or 120 commutation sensor spacing. The
internal low-voltage regulator allows operation over a wide
input voltage range, 20- to 40-V dc.
The Si9979 provides commutation from Hall-effect sensors.
The integral high-side drive, which utilizes combination
bootstrap/charge pump supplies, allows implementation of an
all n-channel MOSFET 3-phase bridge. PWM, direction,
quadrature select, and braking inputs are included for control
along with a tachometer output. Protection features include
cross conduction protection, current limiting, and undervoltage
lockout. The FAULT output indicates when undervoltage, over
current, disable, or invalid sensor shutdown has occurred.
The Si9979 is available in both standard and lead (Pb)-free
48-pin SQFP packages and is specified to operate over the
commercial temperature range of 0 to 70 C (C suffix), and the
industrial temperature range of −40 to 85 C (D suffix).
FUNCTIONAL BLOCK DIAGRAM
Bootstrap Reg.
Low-Voltage
Regulator
V
DD
43
V
DD
V
REF
Low-Side
U.V. Lockout
IN
A
IN
B
IN
C
60/120
EN
F/R
QS
PWM
BRK
TACH
FAULT
1
2
3
4
5
6
7
8
9
10
11
V
DD
V
DD
V
DD
V
DD
V
REF
V
REF
V
REF
V
REF
V
REF
25
13-16, 21-24
37-41, 44-48
V+
42
CAP
A
CAP
B
CAP
C
High-Side
U.V. Lockout
36
34
35
Charge Pump
CAP
A
GT
A
S
A
CAP
B
GT
B
S
B
CAP
C
GT
C
S
C
GB
A
GB
B
GB
C
GND
I
S
−
I
S
+
Bootstrap Reg.
Charge Pump
32
30
31
Bootstrap Reg.
Charge Pump
Input
Logic
V
DD
28
26
27
33
29
R
T
R
T
/C
T
18
17
One Shot
−
+
20
19
Document Number: 70012
S-41209—Rev. E, 21-Jun-04
www.vishay.com
1
Si9979
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS
Voltage on Pin 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 V
Voltage on Pins 1−4, 10, 11 . . . . . . . . . . . . . . . . . . . . .
−0.3
V to V
DD
+ 0.3 V
Voltage on Pins 5−9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
−0.3
V to 5.5 V
Voltage on Pins 26, 28, 30, 32, 34, 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 V
Voltage on Pins 27, 31, 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
−2
to 50 V
Operating Temperature
C Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 70_C
D Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
−40
to 85_C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
−65
to 150_C
Junction Temperature (T
J
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150_C
Power Dissipation (P
D
)
C Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.70 W
D Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.55 W
RECOMMENDED OPERATING RANGE
V+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +20 to 40 V
DC
R
T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 kW Min
SPECIFICATIONS
Test Conditions
Unless Otherwise Specified
Parameter
Power
Supply Voltage Range
Logic Voltage
Supply Current
Logic Current
Internal Reference
d
V+
V
DD
I+
I
DD
V
REF
−20
4.2
−20
mA
v
I
DD
v
0 mA
20
14.5
16
4.5
40
17.5
V
mA
V
Limits
Min
a
Typ
b
Max
a
Unit
Symbol
V+ = 20 to 40 V, I
DD
= 0 mA
Commutation Inputs (IN
A
, IN
B
, IN
C
, 60/120)
High-State
Low-State
High-State Input Current
Low-State Input Current
V
IH
V
IL
I
IH
I
IL
V
IH
= V
DD
V
IL
= 0 V
−50
4.0
1.0
10
V
mA
Logic Inputs (F/R, EN, QS, PWM, BRK)
High-State
Low-State
High-State Input Current
Low-State Input Current
V
IH
V
IL
I
IH
I
IL
V
IH
= 5.5 V
V
IL
= 0 V
−125
2.0
0.8
10
V
mA
Outputs
Low-Side Gate Drive, High State
Low-Side Gate Drive, Low State
High-Side
High Side Gate Drive High State
Drive,
High-Side Gate Drive, Low State
Capacitor Voltage
d
Low-Side Switching, Rise Time
Low-Side Switching, Fall Time
High-Side Switching, Rise Time
High-Side Switching, Fall Time
Break-Before-Make
Break Before Make Time
TACH Output/FAULT Output
TACH Output Pulsewidth
www.vishay.com
V
GBH
V
GBL
V
GTH
V
GTL
V
CAP
t
rL
t
fL
t
rH
t
fH
t
BLH
t
BHL
V
OL
t
T
I
OL
= 1.0 mA
300
Risetime = 1 to 10 V
Falltime = 10 to 1 V
C
L
= 600 pF
V+ = 40 V
55
70
25
100
40
100
300
0.15
600
0.4
V
ns
Document Number: 70012
S-41209—Rev. E, 21-Jun-04
ns
T
A
= 0 to 70_C
T
A
=
−40
to 85_C
C Suffix
D Suffix
16
16
14
16
17.5
0.1
18
20
0.1
V
2
Si9979
Vishay Siliconix
SPECIFICATIONS
Test Conditions
Unless Otherwise Specified
Parameter
Protection
Low-Side Undervoltage Lockout
Low-Side Hysteresis
High-Side Undervoltage Lockout
UVLL
V
H
UVLH
S
A, B, C
= 0 V
12.2
0.8
V
DD
−
3.3
V
Limits
Min
a
Typ
b
Max
a
Unit
Symbol
V+ = 20 to 40 V, I
DD
= 0 mA
Current Limit
Comparator Input Bias Current
Comparator Threshold Voltage
Common Mode Voltage
One Shot Pulse Width
I
IB
V
TH
V
CM
t
p
R
T
= 10 k, C
T
= 0.001
mF
R
T
= 10 k, C
T
= 0.01
mF
T
A
= 0 to 70_C
T
A
=
−40
to 85_C
C Suffix
D Suffix
−5
90
85
0
8
80
10
100
100
100
110
125
1
12
120
mA
mV
V
ms
Notes
a. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum.
b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
c. The reference voltage is not available for external use.
d. V
CAP
= (V+) + (V
DD
).
COMMUTATION TRUTH TABLE
Inputs
Sensors
(60_Spacing)
IN
A
0
1
1
1
0
0
0
1
1
1
0
0
X
X
L
L
L
1
1
0
0
Notes:
Outputs
Top Drive
EN
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
Conditions
Sensors
(120_Spacing)
IN
A
1
1
1
0
0
0
1
1
1
0
0
0
X
X
L
L
L
1
1
0
0
Bottom Drive
GB
A
0
0
0
1
1
0
1
1
0
0
0
0
0
1
1
1
0
0
1
0
1
IN
B
0
0
1
1
1
0
0
0
1
1
1
0
X
X
L
L
L
0
0
1
1
IN
C
0
0
0
1
1
1
0
0
0
1
1
1
X
X
L
L
L
1
1
0
0
IN
B
0
0
1
1
1
0
0
0
1
1
1
0
X
X
L
L
L
1
1
0
0
IN
C
1
0
0
0
1
1
1
0
0
0
1
1
X
X
L
L
L
1
1
0
0
F/R
1
1
1
1
1
1
0
0
0
0
0
0
X
X
X
X
X
X
X
X
X
BR
K
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
0
1
I
S
+
0
0
0
0
0
0
0
0
0
0
0
0
X
X
0
1
1
X
X
X
X
GT- GT- GT-
A
1
1
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
GB
B
1
0
0
0
0
1
0
0
1
1
0
0
0
1
1
1
0
0
1
0
1
GB
C
0
1
1
0
0
0
0
0
0
0
1
1
0
1
1
1
0
0
1
0
1
B
0
0
1
1
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
C
0
0
0
0
1
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
FAULT
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
0
0
0
0
0
0
Disable
Power Down
Brake
Over I in BRK
Over I
L. Any valid sensor combination
X. Don’t care
www.vishay.com
Document Number: 70012
S-41209—Rev. E, 21-Jun-04
3
Si9979
Vishay Siliconix
PIN CONFIGURATION AND ORDERING INFORMATION
SQFP-48
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
V
DD
V+
48 47 46 45 44 43 42 41 40 39 38 37
ORDERING INFORMATION
36
35
34
33
32
31
30
29
28
27
26
25
CAP
A
S
A
GT
A
GB
A
CAP
B
S
B
GT
B
GB
B
CAP
C
S
C
GT
C
GB
C
IN
A
IN
B
IN
C
60/120
EN
F/R
QS
PWM
BRK
TACH
FAULT
GND
1
2
3
4
5
6
7
8
9
10
11
12
13 14 15 16 17 18 19 20 21 22 23 24
GND
GND
I
S
+
I
S
−
GND
GND
GND
GND
GND
R
T
/C
T
GND
R
T
Standard
Part Number
Si9979CS
Si9979DS
Lead (Pb)-Free
Part Number
Si9979CS—E3
Si9979DS—E3
Temperature
Range
Package
0 to 70_C
−40
to 85_C
SQFP-48
NOTE: Si9979CS and Si9979DS are supplied in trays.
Top View
PIN DESCRIPTION
Pins 1−3: IN
A
, IN
B
, IN
C
IN
A
, IN
B
, and IN
C
are the commutation sensor inputs, and are
intended to be driven by open collector Hall effect switches.
These inputs have internal pull up resistors tied to V
DD
, which
eliminates the need for external pull up resistors.
Pin 4: 60/120
The 60/120 input allows the use of the Si9979 with either a 60_
or 120_ commutation sensor spacing. An internal pull up
resistor, which is tied to V
DD
,
sets the default condition to 60_
spacing. 120_ spacing is selected by pulling this input to
ground.
Pin 5: EN (Enable)
A logic “1” on this input allows commutation of the motor. This
is the default condition as this pin is pulled up internally. When
this pin is pulled to ground, all gate drive outputs are turned off.
Pin 6: F/R (Forward/Reverse)
A logic “1” on this input selects commutation for motor rotation
in the “forward” direction. This is the default condition as this
www.vishay.com
pin is pulled up internally. When this pin is pulled to ground, the
commutation sensor logic levels are inverted internally,
causing reverse rotation.
Pin 7: QS (Quadrature Select)
This input determines whether the bottom MOSFETs or both
bottom and top MOSFETs switch in response to the PWM
signal. A logic “1” on this input enables only the bottom
MOSFETs. This is the default condition as this pin is pulled up
internally. When this pin is pulled to ground, both the bottom
and top MOSFETs are enabled.
Pin 8: PWM
An open collector (drain) or TTL compatible signal is applied
to this input to control the motor speed. The QS input
determines which MOSFETs are switched in response to the
PWM signal. If no PWM signal is being used, this input is left
open. It is pulled up internally, which allows the MOSFETs to
follow the commutation sequence.
Document Number: 70012
S-41209—Rev. E, 21-Jun-04
4
Si9979
Vishay Siliconix
PIN DESCRIPTION (CONT’D)
Pin 9: BRK
With this input at logic “1”, the top MOSFETs are turned off and
the bottom MOSFETs are turned on, shorting the motor
windings together. This provides a braking torque which is
dependent on the motor speed. This is the default condition as
this pin is pulled up internally. When this pin is pulled to ground,
the MOSFETs are allowed to follow the commutation
sequence.
Pin 10: TACH
This output provides a minimum 300-nanosecond output
pulse for every commutation sensor transition, yielding a 6
pulse per electrical revolution tachometer signal. This output
is open drain.
Pin 11: FAULT
The FAULT output switches low to indicate that at least one of
the following conditions exists, controller disable (EN),
undervoltage lockout, invalid commutation sensor code
shutdown, or overcurrent shutdown. This output is open drain.
Pin 17: R
T
/C
T
The junction of the current limit one shot timing resistor and
capacitor is connected to this pin. This one-shot is triggered by
the current limit comparator when an overcurrent condition
exists. This action turns off all the gate drives for the period
defined by R
T
and C
T
, thus stopping the flow of current.
Pin 18: R
T
One side of the current limit one shot timing resistor is
connected to this pin.
Pin 19: I
S
+
This is the sensing input of the current limit comparator and
should be connected to the positive side of the current sense
resistor. When the voltage across the current sense resistor
exceeds 100 mV, the comparator switches and triggers the
current limit one-shot. The one-shot turns off all the gate drives
for the period defined by R
T
and C
T
, thus stopping the flow of
current. If the overcurrent condition remains after the
shutdown period, the gate drives will be held off until the
overcurrent condition no longer exists.
Pin 20: I
S
−
This pin is the ground reference for the current limit
comparator. It should be connected directly to the ground side
of the current sense resistor to enhance noise immunity.
Pins 12−16: 21−24, 37−41, 44−48, GND
These pins are the return path for both the logic and gate drive
circuits. Also, they serve to conduct heat out of the package,
into the circuit board.
Pin 25: GB
C
This is the gate drive output for the bottom MOSFET in
Phase C.
Pin 26: GT
C
This is the gate drive output for the top MOSFET in Phase C.
Pin 27: S
C
This pin is negative supply of the high-side drive circuitry. As
such, it is the connection for the negative side of the bootstrap
capacitor, the top MOSFET Source, the bottom MOSFET
Drain, and the Phase C output.
Pin 28: CAP
C
This pin is the positive supply of the high-side circuitry. The
bootstrap capacitor for Phase C is connected between this pin
and SC.
Pin 29: GB
B
This is the gate drive output for the bottom MOSFET in Phase
B.
Pin 30: GT
B
This is the gate drive output for the top MOSFET in Phase B.
Pin 31: S
B
This pin is negative supply of the high-side drive circuitry. As
such, it is the connection for the negative side of the bootstrap
capacitor, the top MOSFET Source, the bottom MOSFET
Drain, and the Phase B output.
Pin 32: CAP
B
This pin is the positive supply of the high-side circuitry. The
bootstrap capacitor for Phase B is connected between this pin
and SB.
Pin 33: GB
A
This is the gate drive output for the bottom MOSFET in
Phase A.
Document Number: 70012
S-41209—Rev. E, 21-Jun-04
www.vishay.com
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
