74LV139
Dual 2-to-4 line decoder/demultiplexer
Rev. 04 — 13 December 2007
Product data sheet
1. General description
The 74LV139 is a low-voltage Si-gate CMOS device that is pin and function compatible
with 74HC139 and 74HCT139.
The 74LV139 is a dual 2-to-4 line decoder/demultiplexer. It has two independent
decoders, each accepting two binary weighted inputs (nA0 and nA1) and providing four
mutually exclusive outputs (nY0 to nY3) that are LOW when selected. Each decoder has
an active LOW input (nE). When nE is HIGH, every output is forced HIGH. The enable
input can be used as the data input for a 1-to-4 demultiplexer application.
2. Features
s
s
s
s
s
s
s
s
s
s
Wide operating voltage: 1.0 V to 5.5 V
Optimized for low voltage applications: 1.0 V to 3.6 V
Accepts TTL input levels between V
CC
= 2.7 V and V
CC
= 3.6 V
Typical output ground bounce < 0.8 V at V
CC
= 3.3 V and T
amb
= 25
°C
Typical HIGH-level output voltage (V
OH
) undershoot: > 2 V at V
CC
= 3.3 V and
T
amb
= 25
°C
Demultiplexing capability
Two independent 2-to-4 line decoders
Multifunction capability
Active LOW mutually exclusive outputs
ESD protection:
x
HBM JESD22-A114E exceeds 2000 V
x
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from
−40 °C
to +85
°C
and from
−40 °C
to +125
°C
s
s
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74LV139N
74LV139D
−40 °C
to +125
°C
−40 °C
to +125
°C
Name
DIP16
SO16
Description
plastic dual in-line package; 16 leads (300 mil)
plastic small outline package; 16 leads;
body width 3.9 mm
Version
SOT38-4
SOT109-1
Type number
NXP Semiconductors
74LV139
Dual 2-to-4 line decoder/demultiplexer
Table 1.
Ordering information
…continued
Package
Temperature range
Name
SSOP16
TSSOP16
Description
plastic shrink small outline package; 16 leads;
body width 5.3 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
Version
SOT338-1
SOT403-1
SOT763-1
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
Type number
74LV139DB
74LV139PW
74LV139BQ
DHVQFN16 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 16 terminals;
body 2.5
×
3.5
×
0.85 mm
4. Functional diagram
1
1E
1Y0
2
3
1A0
1A1
1Y1
1Y2
1Y3
2Y0
14
13
2A0
2A1
2E
15
mna779
4
5
6
7
12
11
10
9
2
3
1
DX 0
0
0 1
G
3
1
2
3
DX 0
0
0 1
G
3
1
2
3
4
5
6
7
2
3
1
1
2
EN
X/Y 0
1
2
3
X/Y 0
1
2
EN
1
2
3
4
5
6
7
12
11
10
9
14
13
15
12
11
10
9
2Y1
2Y2
2Y3
14
13
15
(a)
a) demultiplexer
b) decoder
(b)
mna781
Fig 1. Logic symbol
Fig 2. IEC logic symbol
1Y0
2
3
1A0
1A1
DECODER
1Y1
1Y2
1Y3
1
1E
4
5
6
7
2Y0 12
14
13
2A0
2A1
DECODER
2Y1 11
2Y2 10
2Y3
15
2E
mna780
9
Fig 3. Functional diagram
74LV139_4
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 04 — 13 December 2007
2 of 16
NXP Semiconductors
74LV139
Dual 2-to-4 line decoder/demultiplexer
5. Pinning information
5.1 Pinning
74LV139
1E
1A0
1A1
1Y0
1Y1
1Y2
1Y3
GND
1
2
3
4
16 V
CC
15 2E
1A0
14 2A0
13 2A1
1A1
1Y0
1Y1
1Y2
6
7
8
001aad029
terminal 1
index area
2
3
4
5
6
7
16 V
CC
15 2E
14 2A0
13 2A1
12 2Y0
11 2Y1
10 2Y2
2Y3
9
139
5
12 2Y0
11 2Y1
10 2Y2
9
2Y3
V
CC(1)
8
GND
1Y3
1
1E
001aah107
Transparent top view
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as
a supply pin or input.
Fig 4. Pin configuration DIP16, SO16 and (T)SSOP16
Fig 5. Pin configuration DHVQFN16
5.2 Pin description
Table 2.
Symbol
1E
1A0
1A1
1Y0
1Y1
1Y2
1Y3
GND
2Y3
2Y2
2Y1
2Y0
2A0
2A1
2E
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
14
13
15
16
Description
enable input (active LOW)
address input
address input
output
output
output
output
ground (0 V)
output
output
output
output
address input
address input
enable input (active LOW)
supply voltage
74LV139_4
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 04 — 13 December 2007
3 of 16
NXP Semiconductors
74LV139
Dual 2-to-4 line decoder/demultiplexer
6. Functional description
Table 3.
Function table
H = HIGH voltage level; L = LOW voltage level; X = don’t care
Input
nE
H
L
L
L
L
nA0
X
L
H
L
H
nA1
X
L
L
H
H
Output
nY0
H
L
H
H
H
nY1
H
H
L
H
H
nY2
H
H
H
L
H
nY3
H
H
H
H
L
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
DIP16 package
SO16 package
(T)SSOP16 package
DHVQFN16 package
[1]
[2]
[3]
[4]
[5]
Conditions
V
I
<
−0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
−0.5
V or V
O
> V
CC
+ 0.5 V
V
O
=
−0.5
V to (V
CC
+ 0.5 V)
[1]
[1]
Min
−0.5
-
-
-
-
−50
−65
Max
+7.0
±20
±50
±25
50
-
+150
750
500
500
500
Unit
V
mA
mA
mA
mA
mA
°C
mW
mW
mW
mW
T
amb
=
−40 °C
to +125
°C
[2]
[3]
[4]
[5]
-
-
-
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
P
tot
derates linearly with 12 mW/K above 70
°C.
P
tot
derates linearly with 8 mW/K above 70
°C.
P
tot
derates linearly with 5.5 mW/K above 60
°C.
P
tot
derates linearly with 4.5 mW/K above 60
°C.
74LV139_4
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 04 — 13 December 2007
4 of 16
NXP Semiconductors
74LV139
Dual 2-to-4 line decoder/demultiplexer
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
V
O
T
amb
∆t/∆V
Parameter
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 1.0 V to 2.0 V
V
CC
= 2.0 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 3.6 V to 5.5 V
[1]
Conditions
[1]
Min
1.0
0
0
−40
-
-
-
-
Typ
3.3
-
-
+25
-
-
-
-
Max
5.5
V
CC
V
CC
+125
500
200
100
50
Unit
V
V
V
°C
ns/V
ns/V
ns/V
ns/V
The static characteristics are guaranteed from V
CC
= 1.2 V to V
CC
= 5.5 V, but LV devices are guaranteed to function down to
V
CC
= 1.0 V (with input levels GND or V
CC
).
9. Static characteristics
Table 6.
Static characteristics
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
IH
HIGH-level input voltage
Conditions
V
CC
= 1.2 V
V
CC
= 2.0 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
V
IL
LOW-level input voltage
V
CC
= 1.2 V
V
CC
= 2.0 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
V
OH
HIGH-level output voltage
V
I
= V
IH
or V
IL
I
O
=
−100 µA;
V
CC
= 1.2 V
I
O
=
−100 µA;
V
CC
= 2.0 V
I
O
=
−100 µA;
V
CC
= 2.7 V
I
O
=
−100 µA;
V
CC
= 3.0 V
I
O
=
−100 µA;
V
CC
= 4.5 V
I
O
=
−6
mA; V
CC
= 3.0 V
I
O
=
−12
mA; V
CC
= 4.5 V
-
1.8
2.5
2.8
4.3
2.4
3.6
1.2
2.0
2.7
3.0
4.5
2.82
4.2
-
-
-
-
-
-
-
-
1.8
2.5
2.8
4.3
2.2
3.5
-
-
-
-
-
-
-
V
V
V
V
V
V
V
−40 °C
to +85
°C
Min
0.9
1.4
2.0
0.7V
CC
-
-
-
-
Typ
[1]
-
-
-
-
-
-
-
-
Max
-
-
-
-
0.3
0.6
0.8
0.3V
CC
−40 °C
to +125
°C
Unit
Min
0.9
1.4
2.0
0.7V
CC
-
-
-
-
Max
-
-
-
-
0.3
0.6
0.8
V
V
V
V
V
V
V
0.3V
CC
V
74LV139_4
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 04 — 13 December 2007
5 of 16
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