NSBC115TD
Dual NPN Bias Resistor
Transistors
R1 = 100 kW, R2 =
8
kW
NPN Transistors with Monolithic Bias
Resistor Network
This series of digital transistors is designed to replace a single
device and its external resistor bias network. The Bias Resistor
Transistor (BRT) contains a single transistor with a monolithic bias
network consisting of two resistors; a series base resistor and a
base−emitter resistor. The BRT eliminates these individual
components by integrating them into a single device. The use of a BRT
can reduce both system cost and board space.
Features
www.onsemi.com
MARKING
DIAGRAM
SOT−963
CASE 527AD
AF
M
AFM
1
= Specific Device Code
= Date Code*
•
S and NSV Prefix for Automotive and Other Applications
•
•
•
•
Requiring Unique Site and Control Change Requirements;
AEC-Q101 Qualified and PPAP Capable
Simplifies Circuit Design
Reduces Board Space
Reduces Component Count
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
*Date Code orientation may vary depending upon
manufacturing location.
PIN CONNECTIONS
(3)
R
1
Q
1
Q
2
(2)
(1)
R
2
MAXIMUM RATINGS
(T
A
= 25°C, common for Q1 and Q2, unless otherwise noted)
Rating
Collector−Base Voltage
Collector−Emitter Voltage
Collector Current
−
Continuous
Input Forward Voltage
Input Reverse Voltage
Symbol
V
CBO
V
CEO
I
C
V
IN(fwd)
V
IN(rev)
Max
50
50
100
40
6
Unit
Vdc
Vdc
mAdc
Vdc
Vdc
R
2
(4)
(5)
R
1
(6)
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
ORDERING INFORMATION
Device
NSBC115TDP6T5G
Package
SOT−963
Shipping
†
8,000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and
tape sizes, please refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
©
Semiconductor Components Industries, LLC, 2013
June, 2017
−
Rev. 2
1
Publication Order Number:
DTC115TD/D
NSBC115TD
PACKAGE DIMENSIONS
SOT−963
CASE 527AD
ISSUE E
D
X
Y
4
E
1
2
3
C
SIDE VIEW
6X
A
6
5
H
E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS OF
BASE MATERIAL.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS.
DIM
A
b
C
D
E
e
H
E
L
L2
MILLIMETERS
MIN
NOM
MAX
0.34
0.37
0.40
0.10
0.15
0.20
0.07
0.12
0.17
0.95
1.00
1.05
0.75
0.80
0.85
0.35 BSC
0.95
1.00
1.05
0.19 REF
0.05
0.10
0.15
TOP VIEW
e
L
6X
L2
6X
b
0.08 X Y
BOTTOM VIEW
RECOMMENDED
MOUNTING FOOTPRINT*
0.20
PACKAGE
OUTLINE
6X
0.35
6X
1.20
0.35
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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5
DTC115TD/D
嵌入式系统
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