Area, Profile (0.65 mm) and On-Resistance Per Footprint
Area
APPLICATIONS
• Battery Protection Circuit
- 1-2 Cell Li+/LiP Battery
Pack for Portable Devices
MICRO FOOT
Bump Side View
Backside View
G
1
S
2
5 4
S
2
Pin 1 Identifier
1.8 kΩ
S
1
8904E
xxx
1.8 kΩ
Device Marking:
8904E = P/N Code
xxx = Date/Lot Traceability Code
Ordering Information:
Si8904EDB-T2-E1 (Lead (Pb)-free)
G
2
G
2
6 3
G
1
S
1
1
2
S
1
N-Channel
S
2
ABSOLUTE MAXIMUM RATINGS
T
A
= 25 °C, unless otherwise noted
Parameter
Source1- Source2 Voltage
Gate-Source Voltage
Continuous Source1- Source2 Current (T
J
= 150 °C)
a
Pulsed Source1- Source2 Current
Maximum Power Dissipation
a
Operating Junction and Storage Temperature Range
Package Reflow Conditions
c
IR/Convection
T
A
= 25 °C
T
A
= 85 °C
T
A
= 25 °C
T
A
= 85 °C
Symbol
V
S1S2
V
GS
I
S1S2
I
SM
P
D
T
J
, T
stg
1.7
0.8
- 55 to 150
260
4.9
3.5
25
1
0.5
W
°C
5s
30
± 12
3.8
2.7
A
Steady State
Unit
V
THERMAL RESISTANCE RATINGS
Parameter
Maximum Junction-to-Ambient
a
Maximum Junction-to-Foot
b
t
≤
5s
Steady State
Steady State
Symbol
R
thJA
R
thJF
Typical
60
95
18
Maximum
75
120
22
°C/W
Unit
Notes:
a. Surface Mounted on 1" x 1" FR4 board.
b. The foot is defined as the top surface of the package.
c. Refer to IPC/JEDEC (J-STD-020C), no manual or hand soldering.
Document Number: 72948
S-82119-Rev. C, 08-Sep-08
www.vishay.com
1
Si8904EDB
Vishay Siliconix
SPECIFICATIONS
T
J
= 25 °C, unless otherwise noted
Parameter
Static
Gate Threshold Voltage
Gate-Body Leakage
Zero Gate Voltage Source Current
On-State Source Current
a
V
GS(th)
I
GSS
I
S1S2
I
S(on)
V
SS
= V
GS
, I
D
= 250 µA
V
SS
= 0 V, V
GS
= ± 4.5 V
V
SS
= 0 V, V
GS
= ± 12 V
V
SS
= 30 V, V
GS
= 0 V
V
SS
= 30 V, V
GS
= 0 V, T
J
= 85 °C
V
SS
= 5 V, V
GS
= 4.5 V
V
GS
= 4.5 V, I
SS
= 1 A
V
GS
= 2.5 V, I
SS
= 1 A
V
SS
= 10 V, I
SS
= 1 A
5
0.037
0.048
12
0.045
0.060
0.6
1.6
±4
± 10
1
5
V
µA
mA
µA
A
Ω
S
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
Source1- Source2 On-State Resistance
a
R
S1S2(on)
Forward Transconductance
a
Dynamic
b
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
t
d(on)
t
r
t
d(off)
t
f
g
fs
1.6
V
SS
= 10 V, R
L
= 10
Ω
I
SS
≅
1 A, V
GEN
= 4.5 V, R
g
= 6
Ω
2
1.5
3.7
2.4
3
2.3
5.6
µs
Notes:
a. Pulse test; pulse width
≤
300 µs, duty cycle
≤
2 %.
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
2. Backside surface is coated with a Ag/Ni/Ti layer.
3. Non-solder mask defined copper landing pad.
4. Laser marks on the silicon die back.
Dim.
A
A
1
A
2
b
D
E
e
s
Millimeters
a
Min.
0.600
0.260
0.340
0.370
1.520
2.320
0.750
0.380
Max.
0.650
0.290
0.360
0.410
1.600
2.400
0.850
0.400
Min.
0.0236
0.102
0.0134
0.0146
0.0598
0.0913
0.0295
0.0150
Inches
Max.
0.0256
0.114
0.0142
0.0161
0.0630
0.0945
0.0335
0.0157
Notes:
a. Use millimeters as the primary measurement.
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
Downloading files
The Emulator Startup Server connection server has failed.
Please make sure Emulator Startup Server is running and retry the download by Rebuild All or Update Re ......
EtherCAT（Ethernet for Control Automation Technology）是一种基于以太网的开发构架的实时工业现场总线通讯协议，EtherCAT是最快的工业以太网技术之一，同时它提供纳秒级精确同步。相对于设置了相同循环时间的其他总线系统，EtherCAT系统结构通常能减少25%-30%的CPU负载，EtherCAT的出现为系统的实时性能和拓扑的灵活性树立了新的标准。...[详细]
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
