MR256A08B
FEATURES
•
•
•
•
•
•
•
•
•
3.3 Volt power supply
Fast 35 ns read/write cycle
SRAM compatible timing
Native non-volatility
Unlimited read & write endurance
Data always non-volatile for >20 years at temperature
Commercial and industrial temperatures
All products meet MSL-3 moisture sensitivity level
RoHS-Compliant TSOP2 and BGA packages
32K x 8 MRAM
48-ball FBGA
BENEFITS
•
One memory replaces FLASH, SRAM, EEPROM and MRAM
in system for simpler, more efficient design
•
Improves reliability by replacing battery-backed SRAM
INTRODUCTION
44-pin TSOP2
The
MR256A08B
is a 262,144-bit magnetoresistive random access
memory (MRAM) device organized as 32,768 words of 8 bits. The
MR256A08B offers SRAM compatible 35ns read/write timing with un-
limited endurance.
Data is always non-volatile for greater than 20-years. Data is automatically protected on
power loss by low-voltage inhibit circuitry to prevent writes with voltage out of specification.
The MR256A08B is the ideal memory solution for applications that must permanently store
and retrieve critical data and programs quickly.
The
MR256A08B
is available in a small footprint 400-mil, 44-lead plastic small-outline TSOP
type-2 package, or an 8 mm x 8 mm, 48-pin ball grid array (BGA) package. (The 32-SOIC
package options is obsolete and no longer available for new orders.) All package footprints
are compatible with similar low-power SRAM products and other non-volatile RAM products.
The
MR256A08B
provides highly reliable data storage over a wide range of temperatures.
The product is offered with commercial temperature (0 to +70 °C) and industrial temperature
(-40 to +85 °C) range options.
RoHS
Copyright © 2015 Everspin Technologies
1
MR256A08B Rev. 6.4, 10/2015
MR256A08B
TABLE OF CONTENTS
FEATURES .............................................................................................................................................1
BENEFITS...............................................................................................................................................1
INTRODUCTION ...................................................................................................................................1
BLOCK DIAGRAM AND PIN ASSIGNMENTS .......................................................................................4
Figure 1 – MR256A08B Block Diagram.................................................................................................................. 4
Table 1 – MR256A08B Pin Functions...................................................................................................................... 4
Figure 2 – Pin Diagrams for Available Packages (Top View) 1 ...................................................................... 5
Table 2 – Operating Modes ....................................................................................................................................... 5
ELECTRICAL SPECIFICATIONS ............................................................................................................6
Absolute Maximum Ratings ...........................................................................................................6
Table 3 – Absolute Maximum Ratings................................................................................................................... 6
OPERATING CONDITIONS ...................................................................................................................7
Table 4 – Operating Conditions............................................................................................................................... 7
Power Up and Power Down Sequencing .......................................................................................8
Figure 3 – Power Up and Power Down Sequencing Timing Diagram ....................................................... 8
DC CHARACTERISTICS .........................................................................................................................9
Table 5 – DC Characteristics...................................................................................................................................... 9
Table 6 – Power Supply Characteristics ..............................................................................................................10
TIMING SPECIFICATIONS ................................................................................................................. 11
Table 7 – Capacitance ...............................................................................................................................................11
Table 8 – AC Measurement Conditions ..............................................................................................................11
Figure 4 – Output Load Test Low and High .......................................................................................................11
Figure 5 – Output Load Test All Others ...............................................................................................................11
Read Mode .................................................................................................................................... 12
Table 9 – Read Cycle Timing ...................................................................................................................................12
Copyright © 2015 Everspin Technologies
2
MR256A08B Rev. 6.4, 10/2015
MR256A08B
TABLE OF CONTENTS (CONT’D)
Figure 6 – Read Cycle 1 .............................................................................................................................................12
Figure 7 – Read Cycle 2 .............................................................................................................................................13
Write Mode.................................................................................................................................... 14
Table 10 – Write Cycle Timing 1 (
W
Controlled) ..............................................................................................14
Figure 8 – Write Cycle Timing 1 (
W
Controlled) ..............................................................................................15
Table 11 – Write Cycle Timing 2 (
E
Controlled) ................................................................................................16
Figure 9 – Write Cycle Timing 2 (
E
Controlled) ................................................................................................17
ORDERING INFORMATION ............................................................................................................... 18
Table 12 – Ordering Part Number System for Parallel I/O MRAM..............................................................18
Table 13 – MR256A08B Ordering Part Numbers 1 ..........................................................................................19
PACKAGE OUTLINE DRAWINGS ....................................................................................................... 20
Figure 10 – 44-TSOP2 Package Outline...............................................................................................................20
Figure 11 – 48-BGA Package Outline ...................................................................................................................21
Figure 12 – 32-SOIC Package Outline 1 ..............................................................................................................22
REVISION HISTORY ........................................................................................................................... 23
HOW TO CONTACT US ....................................................................................................................... 24
Copyright © 2015 Everspin Technologies
3
MR256A08B Rev. 6.4, 10/2015
MR256A08B
BLOCK DIAGRAM AND PIN ASSIGNMENTS
Figure 1 – MR256A08B Block Diagram
G
OUTPUT
ENABLE
BUFFER
7
8
ROW
DECODER
COLUMN
DECODER
OUTPUT ENABLE
A[14:0]
15
ADDRESS
BUFFER
E
CHIP
ENABLE
BUFFER
32K x 8 BIT
MEMORY
ARRAY
8
SENSE
AMPS
8
OUTPUT
BUFFER
8
W
WRITE
ENABLE
BUFFER
8
FINAL
WRITE
DRIVERS
8
WRITE
DRIVER
8
DQ[7:0]
WRITE ENABLE
Table 1 – MR256A08B Pin Functions
Signal
Name
A
E
W
G
DQ
V
DD
V
SS
DC
NC
Function
Address Input
Chip Enable
Write Enable
Output Enable
Data I/O
Power Supply
Ground
Do Not Connect
No Connection - Pin 2, 40, 41,43 (TSOP2); Ball C2, C5, D3, F2, F5, G1, G2, G6, H1, H6 (BGA); Pin 9,
24, 31(SOIC) Reserved For Future Expansion
Copyright © 2015 Everspin Technologies
4
MR256A08B Rev. 6.4, 10/2015
MR256A08B
Figure 2 – Pin Diagrams for Available Packages (Top View) 1
DC
A14
A12
A7
A6
A5
A4
V
SS
V
DD
DC
NC
A
A
A
A
A
E
V
DD
V
SS
W
A
A
A
A
A
DC
DC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
DC
NC
DC
NC
NC
A
14
A
13
G
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
DD
NC
W
A13
A8
A9
A11
G
NC
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
NC
NC
NC
A
A
A
V
DD
A
W
A
NC
NC
NC
DQ
1
DC
2
G
DC
NC
DQ
DQ
3
A
A
A
NC
DC
V
SS
4
A
A
A
A
A
14
A
13
5
A
E
NC
DQ
DQ
6
DC
DC
DQ
A
B
C
D
E
F
G
H
A3
NC
A2
A1
A0
DQ0
DQ1
DQ2
V
SS
V
SS
V
DD
DQ
3
V
DD
V
SS
DQ
DC
V
SS
V
DD
A
A
A
DC
DC
NC
NC
44 Pin TSOP2
Note:
32 Pin SOIC 1
48 Pin FBGA
1. The 32-SOIC package is obsolete and shown for legacy reference only. This package option is no longer
available for new orders.
Table 2 – Operating Modes
E
1
H
L
L
L
Notes:
1. H = high, L = low, X = don’t care
2. Hi-Z = high impedance
G1
X
H
L
X
W1
X
H
H
L
Mode
Not selected
Output disabled
Byte Read
Byte Write
V Current
DD
DQ[7:0] 2
Hi-Z
Hi-Z
D
Out
D
in
I ,I
SB1
SB2
I
I
I
DDR
DDR
DDW
Copyright © 2015 Everspin Technologies
5
MR256A08B Rev. 6.4, 10/2015
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
