COM20022I3V-HD: 产品描述Network Controller u0026 Processor ICs ARCNET Contrllr; 产品类别热门应用无线/射频/通信; 文件大小461KB，共74页; 制造商Microchip(微芯科技); 官网地址https://www.microchip.com

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COM20022I3V-HD概述

Network Controller u0026 Processor ICs ARCNET Contrllr

COM20022I3V-HD规格参数

参数名称	属性值
产品种类 Product Category	Network Controller & Processor ICs
制造商 Manufacturer	Microchip(微芯科技)
RoHS	No
产品 Product	ARCNET Controllers
数据速率 Data Rate	10 Mb/s
频率 Frequency	80 MHz
接口类型 Interface Type	RS-485
工作电源电压 Operating Supply Voltage	5 V
工作电源电流 Operating Supply Current	65 mA
最大工作温度 Maximum Operating Temperature	+ 85 C
安装风格 Mounting Style	SMD/SMT
封装 / 箱体 Package / Case	TQFP-48
系列 Packaging	Reel
最小工作温度 Minimum Operating Temperature	- 40 C
工厂包装数量 Factory Pack Quantity	1250
电源电压-最大 Supply Voltage - Max	5.5 V
电源电压-最小 Supply Voltage - Min	4.5 V
单位重量 Unit Weight	0.319998 oz

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COM20022I 3.3V Rev.C

10 Mbps ARCNET (ANSI

878.1) Controller with

2Kx8 On-Chip RAM

Datasheet

Product Features

New Features

−

Data Rates up to 10 Mbps

−

Selectable 8/16 Bit Wide Bus With Data Swapper

−

Programmable Reconfiguration Times

Eight, 256 Byte Pages Allow Four Pages TX and

RX Plus Scratch-Pad Memory

Next ID Readable

Internal Clock Scaler and Clock Multiplier for

Adjusting Network Speed

Operating Temperature Range of -40

C to +85

3.3V power supply with 5V tolerant I/O

Self-Reconfiguration Protocol

Supports up to 255 Nodes

Supports Various Network Topologies (Star,

Tree, Bus...)

CMOS, Single +3.3V Supply

Duplicate Node ID Detection

Powerful Diagnostics

Receive All Packets Mode

Flexible Media Interface:

−

Traditional Hybrid Interface For Long Distances

at 2.5Mbps

−

RS485 Differential Driver Interface For Low Cost,

Low Power, High Reliability

48 Pin TQFP Package; Lead-Free RoHS

Compliant package also available

Ideal for Industrial/Factory/Building Automation

and Transportation Applications

Deterministic, (ANSI 878.1), Token Passing

ARCNET Protocol

Minimal Microcontroller and Media Interface

Logic Required

Flexible Interface For Use With All

Microcontrollers or Microprocessors

Automatically Detects Type of Microcontroller

Interface

2Kx8 On-Chip Dual Port RAM

Command Chaining for Packet Queuing

Sequential Access to Internal RAM

Software Programmable Node ID

ORDERING INFORMATION

Order Number:

COM20022I3V-HD for 48 pin TQFP package

COM20022I3V-HT for 48 pin, TQFP Lead-Free RoHS Compliant package

SMSC COM20022I 3.3V Rev.C

Page 1

Revision 03-08-07

DATASHEET

10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM

Datasheet

80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123

Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete

information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no

responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without

notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does

not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC

or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard

Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors

known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request.

SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause

or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further

testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale

Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems

Corporation (“SMSC”). Product names and company names are the trademarks of their respective holders.

SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES

OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND

ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY

DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR

REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC

OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO

HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH

DAMAGES.

Revision 03-08-07

Page 2

SMSC COM20022I 3.3V Rev.C

DATASHEET

10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM

Datasheet

TABLE OF CONTENTS

Chapter 1

Chapter 2

Chapter 3

Chapter 4

4.1

4.2

4.3

4.4

4.5

4.2.1

General Description ............................................................................................................. 6

Pin Configuration................................................................................................................. 7

Description of Pin Functions ............................................................................................... 8

Protocol Description........................................................................................................... 11

Selecting Clock Frequencies Above 2.5 Mbps .......................................................................................11

Network Protocol ............................................................................................................................... 11

Data Rates......................................................................................................................................... 11

Network Reconfiguration ................................................................................................................... 12

Broadcast Messages......................................................................................................................... 13

Extended Timeout Function .............................................................................................................. 13

4.5.1

4.5.2

4.5.3

Response Time.......................................................................................................................................13

Idle Time.................................................................................................................................................13

Reconfiguration Time..............................................................................................................................13

Invitations To Transmit ...........................................................................................................................14

Free Buffer Enquiries..............................................................................................................................14

Data Packets ..........................................................................................................................................14

Acknowledgements.................................................................................................................................15

Negative Acknowledgements .................................................................................................................15

4.6

Line Protocol ..................................................................................................................................... 13

4.6.1

4.6.2

4.6.3

4.6.4

4.6.5

Chapter 5

5.1

5.2

5.1.1

5.1.2

5.2.1

5.2.2

5.2.3

5.2.4

System Description............................................................................................................. 16

Selection of 8/16-Bit Access ...................................................................................................................19

High Speed CPU Bus Timing Support ....................................................................................................19

Traditional Hybrid Interface.....................................................................................................................21

Backplane Configuration.........................................................................................................................21

Differential Driver Configuration..............................................................................................................23

Programmable TXEN Polarity.................................................................................................................23

Microcontroller Interface.................................................................................................................... 16

Transmission Media Interface ........................................................................................................... 21

Chapter 6

6.1

6.2

6.2.1

6.2.2

6.2.3

6.2.4

6.2.5

6.2.6

6.2.7

6.2.8

6.2.9

6.2.10

6.2.11

6.2.12

6.2.13

6.2.14

Functional Description....................................................................................................... 25

Interrupt Mask Register (IMR) ................................................................................................................27

Data Register..........................................................................................................................................27

Tentative ID Register ..............................................................................................................................27

Node ID Register ....................................................................................................................................28

Next ID Register .....................................................................................................................................28

Status Register .......................................................................................................................................28

Diagnostic Status Register .....................................................................................................................28

Command Register.................................................................................................................................28

Address Pointer Registers ......................................................................................................................29

Configuration Register ........................................................................................................................29

Sub-Address Register .........................................................................................................................29

Setup 1 Register .................................................................................................................................29

Setup 2 Register .................................................................................................................................29

Bus Control Register ...........................................................................................................................30

Sequential Access Memory ....................................................................................................................39

Access Speed.........................................................................................................................................40

Software Interface...................................................................................................................................40

Selecting RAM Page Size.......................................................................................................................40

Transmit Sequence.................................................................................................................................42

Receive Sequence..................................................................................................................................43

Microsequencer................................................................................................................................. 25

Internal Registers .............................................................................................................................. 27

6.3

Internal RAM...................................................................................................................................... 39

6.3.1

6.3.2

6.3.3

6.3.4

6.3.5

6.3.6

6.4

Command Chaining........................................................................................................................... 44

Page 3

Revision 03-08-07

SMSC COM20022I 3.3V Rev.C

DATASHEET

10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM

Datasheet

6.4.1

6.4.2

6.4.3

Transmit Command Chaining .................................................................................................................45

Receive Command Chaining ..................................................................................................................45

Reset Details ..........................................................................................................................................46

Bus Determination ..................................................................................................................................46

Normal Results: ......................................................................................................................................48

Abnormal Results: ..................................................................................................................................48

Oscillator.................................................................................................................................................48

6.5

6.6

Initialization Sequence ...................................................................................................................... 46

6.5.1

6.6.1

6.6.2

6.6.3

Improved Diagnostics........................................................................................................................ 47

Chapter 7

7.1

7.2

Operational Description .................................................................................................... 50

Maximum Guaranteed Ratings* ........................................................................................................ 50

DC Electrical Characteristics............................................................................................................. 50

Chapter 8

Chapter 9

9.1

9.2

Timing Diagrams................................................................................................................ 53

Appendix A ......................................................................................................................... 69

NOSYNC Bit ...................................................................................................................................... 69

EF Bit................................................................................................................................................. 69

Chapter 10

Chapter 11

11.1

Appendix B ...................................................................................................................... 72

Appendix C...................................................................................................................... 73

Software Identification of the COM20022I 3V Rev B and Rev C................................................... 73

Revision 03-08-07

Page 4

SMSC COM20022I 3.3V Rev.C

DATASHEET

10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM

Datasheet

LIST OF FIGURES

Figure 3.1 - COM20022I 3V Operation ........................................................................................................................10

Figure 5.1 - Multiplexed, 8051 - Like Bus Interface with RS-485 Interface .....................................................................17

Figure 5.2 - Non-Multiplexed, 6801-Like Bus Interface with RS-485 Interface ...............................................................18

Figure 5.3 - High Speed CPU Bus Timing – Intel CPU Mode ......................................................................................20

Figure 5.4 - COM20022I 3V Network Using RS-485 Differential Transceivers...............................................................22

Figure 5.5 - Dipluse Waveform for Data of 1-1-0 ...........................................................................................................22

Figure 5.6 - Internal Block Diagram...............................................................................................................................24

Figure 6.1 - Sequential Access Operation.....................................................................................................................39

Figure 6.2 - RAM Buffer Packet Configuration ..............................................................................................................42

Figure 6.3 - Command Chaining Status Register Queue...............................................................................................44

Figure 7.1 - AC Measurements ....................................................................................................................................52

Figure 8.1 - Multiplexed Bus, 68XX-Like Control Signals; Read Cycle ........................................................................53

Figure 8.2 - Multiplexed Bus, 80XX-Like Control Signals; Read Cycle ........................................................................54

Figure 8.3 - Multiplexed Bus, 68XX-Like Control Signals; Write Cycle.........................................................................55

Figure 8.4 - Multiplexed Bus, 80XX-Like Control Signals; Write Cycle.........................................................................56

Figure 8.5 - Non-Multiplexed Bus, 80XX-Like Control Signals; Read Cycle.................................................................57

Figure 8.6 - Non-Multiplexed Bus, 80XX-Like Control Signals; Read Cycle.................................................................58

Figure 8.7 - Non-Multiplexed Bus, 68XX-Like Control Signals; Read Cycle.................................................................59

Figure 8.8 - Non-Multiplexed Bus, 68XX-Like Control Signals; Read Cycle.................................................................60

Figure 8.9 - Non-Multiplexed Bus, 80XX-Like Control Signals; Write Cycle.................................................................61

Figure 8.10 - Non-Multiplexed Bus, 80XX-Like Control Signals; Write Cycle ...............................................................62

Figure 8.11 - Non-Multiplexed Bus, 68XX-Like Control Signals; Write Cycle ...............................................................63

Figure 8.12 - Non-Multiplexed Bus, 68XX-Like Control Signals; Write Cycle ...............................................................64

Figure 8.13 - Normal Mode Transmit or Receive Timing..............................................................................................65

Figure 8.14 - Backplane Mode Transmit or Receive Timing ........................................................................................66

Figure 8.15 - TTL Input Timing on XTAL1 Pin..............................................................................................................67

Figure 8.16 - Reset and Interrupt Timing .....................................................................................................................67

Figure 8.17 - 48 Pin TQFP Package Outline ................................................................................................................68

Figure 9.1 - Effect of the EF Bit on the TA/RI Bit..........................................................................................................71

Figure 10.1 - Example of Interface of Circuit Diagram to ISA Bus................................................................................72

LIST OF TABLES

Table 5.1 - Typical Media .............................................................................................................................................24

Table 6.1 - Read Register Summary............................................................................................................................25

Table 6.2 - Data Register at 16 Bit Access ..................................................................................................................26

Table 6.3 - Write Register Summary ............................................................................................................................26

Table 6.4 - Data Register at 16 Bit Address .................................................................................................................26

Table 6.5 - Status Register ...........................................................................................................................................30

Table 6.6 - Diagnostic Status Register..........................................................................................................................31

Table 6.7 - Command Register.....................................................................................................................................32

Table 6.8 - Address Pointer High Register ....................................................................................................................33

Table 6.9 - Address Pointer Low Register.....................................................................................................................33

Table 6.10 - Sub Address Register ...............................................................................................................................34

Table 6.11 - Configuration Register ..............................................................................................................................34

Table 6.12 - Setup 1 Register .......................................................................................................................................36

Table 6.13 - Setup 2 Register .......................................................................................................................................37

Table 6.14 - Bus Control Register.................................................................................................................................38

Table 8.1 - 48 Pin TQFP Package Parameters ............................................................................................................68

SMSC COM20022I 3.3V Rev.C

Page 5

Revision 03-08-07

DATASHEET

COM20022I3V-HD

COM20022I3V-HD在线购买

COM20022I3V-HD概述

COM20022I3V-HD规格参数

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