PCIX I/O System Clock Generator with EMI Control Features
Features
• Dedicated clock buffer power pins for reduced noise,
crosstalk and jitter
• Input clock frequency of 25 MHz to 33 MHz
• Output frequencies of XINx1, XINx2, XINx3 and XINx4
• One output bank of five clocks
• One REF XIN clock output
• SMBus clock control interface for individual clock
disabling and SSCG control
• Output clock duty cycle is 50% (± 5%)
• < 250 ps skew between output clocks within a bank
• Output jitter <175 ps
• Spread Spectrum feature for reduced electromagnetic
interference (EMI)
• OE pin for entire output bank enable control and
testability
• 28-pin SSOP and TSSOP packages
Table 1. Test Mode Logic Table
[1]
Input Pins
OE
HIGH
HIGH
HIGH
HIGH
LOW
S1
LOW
LOW
HIGH
HIGH
X
S0
LOW
HIGH
LOW
HIGH
X
Output Pins
CLK
XIN
2 * XIN
3 * XIN
4 * XIN
REF
XIN
XIN
XIN
XIN
Three-state Three-state
Block Diagram
Pin Configuration
REF
1
2
3
4
5
6
28
27
26
25
24
23
SDATA
SCLK
VSS
VDDP
CLK0
CLK1
CLK2
VSS
VDDP
CLK3
CLK4
VDDA
VSS
SSCG#
VDD
XIN
XOUT
VSS
S0
S1
GOOD#
VSS
IA0
IA1
IA2
VDDA
OE
SSCG#
SSCG
Logic
/N
1
0
CLK0
CLK1
CLK2
CLK3
CLK4
OE
GOOD#
REF
C9531
XIN
XOUT
7
8
9
10
11
12
13
14
22
21
20
19
18
17
16
15
SDATA
SCLK
IA(0:2)
S(0,1)
I
2
C
Control
Logic
Note:
1. XIN is the frequency of the clock on the device’s XIN pin.
.......................... Document #: 38-07034 Rev. *E Page 1 of 9
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C9531
Pin Description
[3]
Pin
[2]
3
4
1
14*
24, 23, 22, 19, 18
8
XIN
XOUT
REF
OE
CLK(0:4)
GOOD#
Name
PWR
[4]
VDDA
VDDA
VDD
VDD
VDDP
VDD
I/O
I
O
O
I
O
O
Description
Crystal Buffer Input Pin.
Connects to a crystal, or an external clock
source. Serves as input clock TCLK, in Test mode.
Crystal Buffer Output Pin.
Connects to a crystal only. When a Can
Oscillator is used or in test mode, this pin is kept unconnected.
Buffered inverted outputs of the signal applied at Xin, typically
33.33 or 25.0 MHz.
Output Enable for Clock Bank.
Causes the CLK (0:4) output clocks
to be in a three-state condition when driven to a logic low level.
A bank of five XINx1, XINx2, XINx3 and XINx4 output clocks.
When his output signal is a logic low level, it indicates that the
output
clocks of the bank are locked to the input reference clock.
This
output is latched.
Clock Bank Selection Bits.
These control the clock frequency that will
be present on the outputs of the bank of buffers. See table on page
one for frequency codes and selection values.
3.3V common power supply pin for all PCI clocks CLK (0:4).
SMBus Address Selection Input Pins.
See
Table 3
on page 3.
Spread Spectrum Clock Generator.
Enables Spread Spectrum clock
modulation when at a logic low level, see Spread Spectrum Clocking
on page 6.
Data for the Internal SMBus Circuitry.
See
Table 3
on page 3.
Clock for the Internal SMBus Circuitry.
See
Table 3
on page 3.
Power for Internal Analog Circuitry.
This supply should have a
separately decoupled current source from VDD.
Power supply for internal core logic.
Ground pins for the device.
6*, 7*
S(0,1)
VDD
I
20, 25
10*, 11*, 12*
15*
VDDP
IA(0:2)
SSCG#
VDD
VDD
PWR
I
I
28
27
13, 17
2
5, 9, 16, 21, 26
SDATA
SCLK
VDDA
VDD
VSS
VDD
VDD
I/O
I
I
PWR
PWR
Notes:
2. Pin numbers ending with * indicate that they contain device internal pull-up resistors that will insure that they are sensed as a logic 1 if no external circuitry is
connected to them.
3. A bypass capacitor (0.1F) should be placed as close as possible to each V
DD
pin. If these bypass capacitors are not close to the pins their high frequency filtering
characteristic will be cancelled by the lead inductance of the trace.
4. PWR = Power connection, I = Input, O = Output and I/O = both input and output functionality of the pin(s).
..........................Document #: 38-07034 Rev. *E Page 2 of 9
C9531
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initializes to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required.
Table 2. Block Read and Block Write Protocol
Block Write Protocol
Bit
1
2:8
9
10
11:18
19
20:27
28
29:36
37
38:45
46
....
....
....
....
....
....
Start
Slave address – 7 bits
Write = 0
Acknowledge from slave
Command Code – 8 bits
'00000000' stands for block operation
Acknowledge from slave
Byte Count – 8 bits
Acknowledge from slave
Data byte 1 – 8 bits
Acknowledge from slave
Data byte 2 – 8 bits
Acknowledge from slave
......................
Data Byte (N–1) – 8 bits
Acknowledge from slave
Data Byte N – 8 bits
Acknowledge from slave
Stop
Description
Data Protocol
The clock driver serial protocol accepts block write a opera-
tions from the controller. The bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. The C9531 does not support the Block Read
function.
The block write protocol is outlined in
Table 2.
The addresses
are listed in
Table 3.
Table 3. SMBus Address Selection Table
SMBus Address of the Device
DE
DC
DA
D8
D6
D4
D0
D2
IA0 Bit (Pin 10)
0
1
0
1
0
1
0
1
IA1 Bit (Pin 11)
0
0
1
1
0
0
1
1
IA2 Bit (Pin 12)
0
0
0
0
1
1
1
1
..........................Document #: 38-07034 Rev. *E Page 3 of 9
C9531
Serial Control Registers
Byte 0: Output Register
Bit
7
6
5
4
3
2
1
0
@Pup
1
0
1
0
0
0
0
1
HWSEL
Name
TESTEN
SSEN
SSSEL
S1
S0
Description
Test Mode Enable.
1 = Normal operation, 0 = Test mode
Spread Spectrum modulation control bit (effective only when Bit 0 of this register is
set to a 0) 0 = OFF, 1= ON
SSCG Spread width select. 1 = 0.5%, 0 = 1.0% See
Table 4
below for clarification
S1 Bank MSB frequency control bit (effective only when Bit 0 of this register is set
to a 0)
S0 Bank LSB frequency control bit (effective only when Bit 0 of this register is set
to a 0)
Not used
Not used
Hardware/SMBus frequency control. 1 = Hardware (pins 6, 7, and 15), 0 = SMBus
Byte 0 bits 3, 4, & 6
Table 4. Clarification Table for Byte0, bit 5
Byte0, bit6
0
0
1
1
Table 5. Test Table
Outputs
Test Function Clock
Frequency
Byte 1: CPU Register
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
1
1
1
1
REFEN
Name
Reserved
Reserved
REF Output Enable
0 = Disable, 1= Enable
Reserved
Reserved
Reserved
Reserved
Reserved
Description
CLK
XIN/4
REF
XIN
Note
XIN is the frequency of the clock that is present on the
XIN input during test mode.
Byte0, bit5
0
1
0
1
Frequency generated from XIN
Spread @ –1.0%
Spread @ –0.5%
Description
Frequency generated from second PLL
Byte 2: PCI Register
Bit
7
6
5
4
@Pup
1
1
1
1
18
Name
Reserved
Reserved
Reserved
CLK4 Output Enable
0 = Disable, 1= Enable
Description
..........................Document #: 38-07034 Rev. *E Page 4 of 9
C9531
Byte 2: PCI Register
(continued)
Bit
3
2
1
0
@Pup
1
1
1
1
Name
19
22
23
24
CLK3 Output Enable
0 = Disable, 1= Enable
CLK2Output Enable
0 = Disable, 1= Enable
CLK1 Output Enable
0 = Disable, 1= Enable
CLK0 Output Enable
0 = Disable, 1= Enable
control signals is determined by the SMBus register Byte 0 bit
0. At initial power up this bit is set of a logic 1 state and thus
the frequency selections are controlled by the logic levels
present on the device’s S(0,1) pins. If the application does not
use an SMBus interface then hardware frequency selection
S(0,1) must be used. If it is desired to control the output clocks
using an SMBus interface, then this bit (B0b0) must first be set
to a low state. After this is done the device will use the contents
of the internal SMBus register Bytes 0 bits 3 and 4 to control
the output clock’s frequency.
The following formula and schematic may be used to under-
stand and calculate either the loading specification of a crystal
for a design or the additional discrete load capacitance that
must be used to provide the correct load to a known load rated
crystal.
Description
Output Clock Three-state Control
All of the clocks in the Bank may be placed in a three-state
condition by bringing their relevant OE pins to a logic low state.
This transition to and from a three-state and active condition
is a totally asynchronous event and clock glitching may occur
during the transitioning states. This function is intended as a
board level testing feature. When output clocks are being
enabled and disabled in active environments the SMBus
control register bits are the preferred mechanism to control
these signals in an orderly and predictable manner.
The output enable pin contains an internal pull-up resistor that
will insure that a logic 1 is maintained and sensed by the
device if no external circuitry is connected to this pin.
Output Clock Frequency Control
All of the output clocks have their frequency selected by the
logic state of the S0 and S1 control bits. The source of these
C
L
=
where:
C
XTAL
C
XINFTG
C
XINPCB
C
XINDISC
(C
XINPCB
+ C
XINFTG
+ C
XINDISC
)
x
(C
XOUTPCB
) + C
XOUTFTG
) + C
XOUTDISC
)
(C
XINPCB
+ C
XINFTG
+ C
XINDISC
)
+
(C
XOUTPCB
) + C
XOUTFTG
) + C
XOUTDISC
)
= The load rating of the crystal.
= The clock generators XIN pin effective device internal capacitance to ground.
= The effective capacitance to ground of the crystal to device PCB trace.
= Any discrete capacitance that is placed between the XIn pin and ground.
C
XOUTFTG
= The clock generators XOUT pin effective device internal capacitance to ground.
C
XOUTPCB
= The effective capacitance to ground of the crystal to device PCB trace.
C
XOUTDISC
= Any discrete capacitance that is placed between the XIn pin and ground.
C
XINPCB
C
XOUTPCB
C
XINDISC
C
XOUTDISC
XIN
C
XINFTG
C
XOUTFTG
XOUT
Clock Generator
..........................Document #: 38-07034 Rev. *E Page 5 of 9
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