Data Sheet No. PD60238 revE
IRS2153(1)D(S)PbF
SELF-OSCILLATING HALF-BRIDGE DRIVER IC
Features
Integrated 600 V half-bridge gate driver
C
T
, R
T
programmable oscillator
15.4 V Zener clamp on V
CC
Micropower startup
Non-latched shutdown on C
T
pin (1/6th V
CC
)
Internal bootstrap FET
Excellent latch immunity on all inputs and outputs
+/- 50 V/ns dV/dt immunity
ESD protection on all pins
8-lead SOIC or PDIP package
Internal deadtime
Product Summary
V
OFFSET
Duty cycle
Driver source/sink
current
V
clamp
Deadtime
600 V Max
50%
180 mA/260 mA typ.
15.4 V typ.
1.1
µs
typ. (IRS2153D)
0.6
µs
typ. (IRS21531D)
Description
The IRS2153(1)D is based on the popular IR2153 self-
oscillating half-bridge gate driver IC using a more
advanced silicon platform, and incorporates a high
voltage half-bridge gate driver with a front end oscillator
similar to the industry standard CMOS 555 timer. HVIC
and latch immune CMOS technologies enable rugged
monolithic construction. The output driver features a high
pulse current buffer stage designed for minimum driver
cross-conduction. Noise immunity is achieved with low
di/dt peak of the gate drivers.
Package
PDIP8
IRS2153(1)DPbF
SO8
IRS2153(1)DSPbF
Typical Connection Diagram
+ AC Rectified Line
RVCC
VCC
1
8
VB
CBOOT
MHS
IRS2153(1)D
RT
2
7
HO
RT
CT
CVCC
CT
COM
3
6
VS
L
RL
4
5
LO
MLS
- AC Rectified Line
1
IRS2153(1)D
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All
voltage parameters are absolute voltages referenced to COM, all currents are defined positive into any lead.
The thermal resistance and power dissipation ratings are measured under board mounted and still air
conditions.
Symbol
V
B
V
S
V
HO
V
LO
I
RT
V
RT
V
CT
I
CC
I
OMAX
dV
S
/dt
P
D
P
D
R
thJA
R
thJA
T
J
T
S
T
L
Parameter
Definition
High side floating supply voltage
High side floating supply offset voltage
High side floating output voltage
Low side output voltage
R
T
pin current
R
T
pin voltage
C
T
pin voltage
Supply current (Note 1)
Maximum allowable current at LO and HO due to external
power transistor Miller effect.
Allowable offset voltage slew rate
Maximum power dissipation @ T
A
≤
+25 ºC, 8-Pin DIP
Maximum power dissipation @ T
A
≤
+25 ºC, 8-Pin SOIC
Thermal resistance, junction to ambient, 8-Pin DIP
Thermal resistance, junction to ambient, 8-Pin SOIC
Junction temperature
Storage temperature
Lead temperature (soldering, 10 seconds)
Min.
-0.3
V
B
- 25
V
S
– 0.3
-0.3
-5
-0.3
-0.3
---
-500
-50
---
---
---
---
-55
-55
---
Max.
625
V
B
+ 0.3
V
B
+ 0.3
V
CC
+ 0.3
5
V
CC
+ 0.3
V
CC
+ 0.3
20
500
50
1.0
0.625
85
128
150
150
300
Units
V
mA
V
mA
V/ns
W
ºC/W
ºC
Note 1:
This IC contains a zener clamp structure between the chip V
CC
and COM which has a nominal
breakdown voltage of 15.4 V. Please note that this supply pin should not be driven by a DC, low
impedance power source greater than the V
CLAMP
specified in the Electrical Characteristics section.
2
IRS2153(1)D
Recommended Operating Conditions
For proper operation the device should be used within the recommended conditions.
Symbol
V
BS
V
S
V
CC
I
CC
T
J
Parameter
Definition
High side floating supply voltage
Steady state side floating supply offset voltage
Supply voltage
Supply current
Junction temperature
Min.
V
CC
- 0.7
-3.0 (Note 2)
V
CCUV+
+0.1 V
(Note 3)
-40
Max.
V
CLAMP
600
V
CC CLAMP
5
125
Units
V
mA
ºC
Note 2:
It is recommended to avoid output switching conditions where the negative-going spikes at the V
S
node would decrease V
S
below ground by more than -5 V.
Note 3:
Enough current should be supplied to the V
CC
pin of the IC to keep the internal 15.6 V zener diode
clamping the voltage at this pin.
Recommended Component Values
Symbol
R
T
C
T
Parameter
Component
Timing resistor value
C
T
pin capacitor value
Min.
1
330
Max.
---
---
Units
kΩ
pF
V
BIAS
(V
CC
, V
BS
)
= 14 V, V
S
=0 V and T
A
= 25 °C, CLO = CHO = 1 nF.
Frequency vs. RT
1,000,000
CT Values
100,000
Frequency (Hz)
10,000
1,000
100
10
1,000
330pf
470pF
1nF
2.2nF
4.7nF
10nF
10,000
100,000
1,000,000
RT (Ohm)
For further information, see Fig. 12.
3
IRS2153(1)D
Electrical Characteristics
V
BIAS
(V
CC
, V
BS
)
= 14 V, C
T
= 1 nF, V
S
=0 V and T
A
= 25 °C unless otherwise specified. The output voltage and current (V
O
and I
O
)
parameters are
referenced to COM and are applicable to the respective output leads: HO or LO. CLO = CHO = 1 nF.
Symbol
V
CCUV+
V
CCUV-
V
CCUVHYS
I
QCCUV
I
QCC
I
CC
V
CC
CLAMP
I
QBS
V
BSUV+
V
BSUV-
I
LK
Definition
Rising V
CC
undervoltage lockout threshold
Falling V
CC
undervoltage lockout threshold
V
CC
undervoltage lockout hysteresis
Micropower startup V
CC
supply current
Quiescent V
CC
supply current
V
CC
supply current
V
CC
zener clamp voltage
Quiescent V
BS
supply current
V
BS
supply undervoltage positive going
threshold
V
BS
supply undervoltage negative going
threshold
Offset supply leakage current
Min
10.0
8.0
1.6
---
---
---
14.4
---
8.0
7.0
---
18.4
88
---
---
0.20
---
---
2.2
---
---
---
---
---
---
Typ
11.0
9.0
2.0
130
800
1.8
15.4
60
9.0
8.0
---
19.0
93
50
0.02
Max
12.0
10.0
2.4
170
1000
---
16.8
80
9.5
Units
Test Conditions
Low Voltage Supply Characteristics
V
V
CC
≤
V
CCUV-
R
T
= 36.9 kΩ
I
CC
= 5 mA
µA
mA
V
µA
Floating Supply Characteristics
V
9.0
50
19.6
100
---
1.0
0.6
---
---
2.4
50
300
50
300
100
50
300
mV
I
RT
= -100
µA
I
RT
= -1 mA
I
RT
= 100
µA
I
RT
= 1 mA
V
CC
≤
V
CCUV-
I
RT
= -100
µA,
V
CT
= 0 V
µA
V
B
= V
S
= 600 V
R
T
= 36.5 kΩ
R
T
= 7.15 kΩ
f
o
< 100 kHz
V
CC
= 7 V
Oscillator I/O Characteristics
f
OSC
d
I
CT
I
CTUV
V
CT+
V
CT-
V
CTSD
V
RT+
V
RT-
V
RTUV
Oscillator frequency
R
T
pin duty cycle
C
T
pin current
UV-mode C
T
pin pulldown current
Upper C
T
ramp voltage threshold
Lower C
T
ramp voltage threshold
C
T
voltage shutdown threshold
High-level R
T
output voltage, V
CC
- V
RT
Low-level R
T
output voltage
UV-mode R
T
output voltage
kHz
%
µA
mA
V
0.30
9.32
4.66
2.3
10
100
10
100
0
10
100
V
RTSD
SD-mode R
T
output voltage, V
CC
- V
RT
---
I
RT
= -1 mA,
V
CT
= 0 V
4
IRS2153(1)D
Electrical Characteristics
V
BIAS
(V
CC
, V
BS)
= 14 V, C
T
= 1 nF, V
S
=0 V and T
A
= 25 °C unless otherwise specified. The output voltage and current (V
O
and I
O
)
parameters are referenced to COM and are applicable to the respective output leads: HO or LO. CLO = CHO = 1 nF.
Symbol
V
OH
V
OL
V
OL_UV
t
r
t
f
t
sd
t
d
t
d
I
O+
I
O-
Definition
High-level output voltage
Low-level output voltage
UV-mode output voltage
Output rise time
Output fall time
Shutdown propagation delay
Output deadtime (HO or LO) (IRS2153D)
Output deadtime (HO or LO) (IRS21531D)
Output source current
Output sink current
Min
---
---
---
---
---
---
0.65
0.35
---
---
Typ
V
CC
COM
COM
120
50
350
1.1
0.6
180
260
Max
---
---
---
220
80
---
1.75
0.85
---
---
Units
Test Conditions
Gate Driver Output Characteristics
I
O
= 0 A
V
I
O
= 0 A,
V
CC
≤
V
CCUV-
ns
µs
µs
mA
Bootstrap FET Characteristics
V
B_ON
I
B_CAP
I
B_10V
V
B
when the bootstrap FET is on
V
B
source current when FET is on
V
B
source current when FET is on
---
40
10
13.7
55
12
---
---
---
V
mA
C
BS
=0.1 uF
V
B
=10 V
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
