Low Skew, 1-to-4, LVCMOS/ LVTTL-to-LVDS
Fanout Buffer
Datasheet
854105I
General Description
The 854105I is a low skew, high performance 1-to-4
LVCMOS/LVTTL-to-LVDS Clock Fanout Buffer. Utilizing Low Voltage
Differential Signaling (LVDS), the 854105I provides a low power, low
noise solution for distributing clock signals over controlled
impedances of 100. The 854105I accepts an LVCMOS/LVTTL
input level and translates it to LVDS output levels.
Guaranteed output and part-to-part skew characteristics make the
854105I ideal for those applications demanding well defined
performance and repeatability.
Features
•
•
•
•
•
•
•
•
•
•
•
•
Four differential LVDS output pairs
One single-ended LVCMOS/LVTTL input
CLK can accept the following input levels: LVCMOS, LVTTL
Maximum output frequency: 250MHz
Translates single-ended input signals to LVDS levels
Additive phase jitter, RMS: 0.16ps (typical)
Output skew: 72ps (maximum)
Part-to-part skew: 350ps (maximum)
Propagation delay: 1.75ns (maximum)
3.3V operating supply
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
Q0
nQ0
Pullup
Pin Assignment
OE0
OE1
OE2
V
DD
GND
CLK
nc
OE3
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
OE0
Q1
nQ1
CLK
Pulldown
Pullup
OE1
Q2
nQ2
854105I
16-Lead TSSOP
4.4mm x 5.0mm x 0.925mm package body
G Package
Top View
Pullup
OE2
Q3
nQ3
Pullup
OE3
©2016 Integrated Device Technology, Inc.
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Revision B, February 23, 2016
854105I Datasheet
Pin Description and Pin Characteristics
Table 1. Pin Descriptions
Number
1
2
3
4
5
6
7
8
9, 10
11, 12
13, 14
15, 16
Name
OE0
OE1
OE2
V
DD
GND
CLK
nc
OE3
nQ3, Q3
nQ2, Q2
nQ1, Q1
nQ0, Q0
Input
Input
Input
Power
Power
Input
Unused
Input
Output
Output
Output
Output
Pullup
Pulldown
Type
Pullup
Pullup
Pullup
Description
Output enable pin for Q0, nQ0 outputs. See Table 3. LVCMOS/LVTTL interface levels.
Output enable pin for Q1, nQ1 outputs. See Table 3. LVCMOS/LVTTL interface levels.
Output enable pin for Q2, nQ2 outputs. See Table 3. LVCMOS/LVTTL interface levels.
Positive supply pin.
Power supply ground.
Single-ended clock input. LVCMOS/LVTTL interface levels.
No connect.
Output enable pin for Q3, nQ3 outputs. See Table 3. LVCMOS/LVTTL interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
k
Function Table
Table 3. Output Enable Function Table
Inputs
OE[3:0]
0
1
Outputs
Q[3:0], nQ[3:0]
High-Impedance
Active (default)
©2016 Integrated Device Technology, Inc.
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Revision B, February 23, 2016
854105I Datasheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics or AC
Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
(LVDS)
Continuos Current
Surge Current
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
10mA
15mA
100.3°C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. LVDS Power Supply DC Characteristics,V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
I
DD
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
75
Units
V
mA
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
CLK
Input High Current
OE[3:0]
CLK
I
IL
Input Low Current
OE[3:0]
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-5
-150
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
150
5
Units
V
V
µA
µA
µA
µA
Table 4C. LVDS DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
OD
V
OD
V
OS
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
1.15
1.3
Test Conditions
Minimum
250
Typical
350
Maximum
450
50
1.5
50
Units
mV
mV
V
mV
©2016 Integrated Device Technology, Inc.
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Revision B, February 23, 2016
854105I Datasheet
Table 5. AC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
f
MAX
t
PD
tjit
tsk(o)
tsk(pp)
t
R
/ t
F
odc
Parameter
Output Frequency
Propagation Delay; NOTE 1
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter
Section
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
ƒ
100MHz
100 < ƒ
200MHz
115
45
40
155.52MHz,
Integration Range: (12kHz – 20MHz)
0.9
0.16
72
350
715
55
60
Test Conditions
Minimum
Typical
Maximum
250
1.75
Units
MHz
ns
ps
ps
ps
ps
%
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: All parameters measured at f
MAX
unless noted otherwise.
NOTE 1: Measured from V
DD
/2 of the input to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential
crossing point.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature and with equal load
conditions. Using the same type of input on each device, the outputs are measured at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
©2016 Integrated Device Technology, Inc.
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Revision B, February 23, 2016
854105I Datasheet
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the
dBc Phase
Noise.
This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a
dBc
value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
Additive Phase Jitter @ 155.52MHz
12kHz to 20MHz = 0.16ps (typical)
SSB Phase Noise dBc/Hz
Offset from Carrier Frequency (Hz)
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device. This
is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
The source generator "Rohde & Schwarz SMA100 Signal Generator
as external input to an Agilent 8133A 3GHz Pulse Generator".
©2016 Integrated Device Technology, Inc.
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Revision B, February 23, 2016
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