CY7C109D
CY7C1009D
1-Mbit (128 K × 8) Static RAM
1-Mbit (128 K × 8) Static RAM
Features
■
■
Pin- and function-compatible with CY7C109B/CY7C1009B
High speed
❐
t
AA
= 10 ns
Low active power
❐
I
CC
= 80 mA at 10 ns
Low CMOS standby power
❐
I
SB2
= 3 mA
2.0 V Data Retention
Automatic power-down when deselected
TTL-compatible inputs and outputs
Easy memory expansion with CE
1
, CE
2
and OE options
CY7C109D available in Pb-free 32-pin 400-Mil wide Molded
SOJ and 32-pin TSOP I packages. CY7C1009D available in
Pb-free 32-pin 300-Mil wide Molded SOJ package
(OE), and tri-state drivers.The eight input and output pins (I/O
0
through I/O
7
) are placed in a high-impedance state when:
■
■
■
Deselected (CE
1
HIGH or CE
2
LOW),
Outputs are disabled (OE HIGH),
When the write operation is active (CE
1
LOW, CE
2
HIGH, and
WE LOW)
■
■
■
■
■
■
■
Write to the device by taking Chip Enable One (CE
1
) and Write
Enable (WE) inputs LOW and Chip Enable Two (CE
2
) input
HIGH. Data on the eight I/O pins (I/O
0
through I/O
7
) is then
written into the location specified on the address pins (A
0
through
A
16
).
Read from the device by taking Chip Enable One (CE
1
) and
Output Enable (OE) LOW while forcing Write Enable (WE) and
Chip Enable Two (CE
2
) HIGH. Under these conditions, the
contents of the memory location specified by the address pins
appears on the I/O pins.
The CY7C109D/CY7C1009D device is suitable for interfacing
with processors that have TTL I/P levels. It is not suitable for
processors that require CMOS I/P levels. Please see
Electrical
Characteristics on page 4
for more details and suggested
alternatives.
For a complete list of related documentation, click
here.
Functional Description
The CY7C109D/CY7C1009D
[1]
is a high-performance CMOS
static RAM organized as 131,072 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE
1
), an
active HIGH Chip Enable (CE
2
), an active LOW Output Enable
Logic Block Diagram
INPUT BUFFER
A0
A1
A2
A3
A4
A5
A6
A7
A8
IO0
IO1
ROW DECODER
128K x 8
ARRAY
SENSE AMPS
IO2
IO3
IO4
IO5
IO6
CE1
CE2
WE
OE
COLUMN DECODER
POWER
DOWN
IO7
A9
A10
A11
A12
A13
A14
A15
A16
Cypress Semiconductor Corporation
Document Number: 38-05468 Rev. *J
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised January 16, 2015
CY7C109D
CY7C1009D
Contents
Pin Configurations ........................................................... 3
Selection Guide ................................................................ 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
Electrical Characteristics ................................................. 4
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
AC Test Loads and Waveforms ....................................... 5
Data Retention Characteristics ....................................... 6
Data Retention Waveform ................................................ 6
Switching Characteristics ................................................ 7
Switching Waveforms ...................................................... 8
Truth Table ...................................................................... 11
Ordering Information ...................................................... 11
Ordering Code Definitions ......................................... 11
Package Diagrams .......................................................... 12
Acronyms ........................................................................ 14
Document Conventions ................................................. 14
Units of Measure ....................................................... 14
Document History Page ................................................. 15
Sales, Solutions, and Legal Information ...................... 16
Worldwide Sales and Design Support ....................... 16
Products .................................................................... 16
PSoC® Solutions ...................................................... 16
Cypress Developer Community ................................. 16
Technical Support ..................................................... 16
Note
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at
www.cypress.com.
Document Number: 38-05468 Rev. *J
Page 2 of 16
CY7C109D
CY7C1009D
Pin Configurations
Figure 1. 32-pin TSOP I pinout
A
11
A
9
A
8
A
13
WE
CE
2
A
15
V
CC
NC
A
16
A
14
A
12
A
7
A
6
A
5
A
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A
10
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
GND
I/O
2
I/O
1
I/O
0
A
0
A
1
A
2
A
3
Figure 2. 32-pin SOJ pinout (Top View)
[2]
NC
A
16
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A
15
CE
2
WE
A
13
A
8
A
9
A
11
OE
A
10
CE
1
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
TSOP I
Top View
(not to scale)
Selection Guide
Description
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
CY7C109D-10
CY7C1009D-10
10
80
3
Unit
ns
mA
mA
Note
2. NC pins are not connected on the die.
Document Number: 38-05468 Rev. *J
Page 3 of 16
CY7C109D
CY7C1009D
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage Temperature ............................... –65
C
to +150
C
Ambient Temperature with
Power Applied ......................................... –55 °C to +125 °C
Supply Voltage on
V
CC
to Relative GND
[3]
...............................–0.5 V to +6.0 V
DC Voltage Applied to Outputs
in High-Z State
[3]
................................ –0.5 V to V
CC
+ 0.5 V
DC Input Voltage
[3]
............................ –0.5 V to V
CC
+ 0.5 V
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage
(per MIL-STD-883, Method 3015) .......................... > 2001 V
Latch-up Current .................................................... > 200 mA
Operating Range
Range
Industrial
Ambient
Temperature
–40 °C to +85 °C
V
CC
5 V
0.5 V
Speed
10 ns
Electrical Characteristics
Over the Operating Range
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
[3]
Input Leakage Current
Output Leakage Current
V
CC
Operating Supply Current
GND < V
I
< V
CC
GND < V
I
< V
CC
, Output Disabled
V
CC
= Max, I
OUT
= 0 mA,
f = f
max
= 1/t
RC
100 MHz
83 MHz
66 MHz
40 MHz
I
SB1
I
SB2
Automatic CE Power-Down
Current – TTL Inputs
Automatic CE Power-Down
Current – CMOS Inputs
Max V
CC
, CE
1
> V
IH
or CE
2
< V
IL
,
V
IN
> V
IH
or V
IN
< V
IL
, f = f
max
Max V
CC
, CE
1
> V
CC
– 0.3 V, or CE
2
< 0.3 V,
V
IN
> V
CC
– 0.3 V, or V
IN
< 0.3 V, f = 0
I
OH
= –4.0 mA
I
OH
= –0.1mA
I
OL
= 8.0 mA
2.2
–0.5
–1
–1
–
–
–
–
–
–
Test Conditions
7C109D-10
7C1009D-10
Min
2.4
–
Max
–
3.4
[4]
0.4
V
CC
+ 0.5
0.8
+1
+1
80
72
58
37
10
3
V
V
V
A
A
mA
mA
mA
mA
mA
mA
V
Unit
Note
3. V
IL
(min) = –2.0 V and V
IH
(max) = V
CC
+ 1 V for pulse durations of less than 5 ns.
4. Please note that the maximum V
OH
limit does not exceed minimum CMOS V
IH
of 3.5 V. If you are interfacing this SRAM with 5 V legacy processors that require a
minimum V
IH
of 3.5 V, please refer to Application Note
AN6081
for technical details and options you may consider.
Document Number: 38-05468 Rev. *J
Page 4 of 16
CY7C109D
CY7C1009D
Capacitance
Parameter
[5]
C
IN
C
OUT
Description
Input capacitance
Output capacitance
Test Conditions
T
A
= 25 °C, f = 1 MHz, V
CC
= 5.0 V
Max
8
8
Unit
pF
pF
Thermal Resistance
Parameter
[5]
JA
JC
Description
Thermal resistance
(junction to ambient)
Thermal resistance
(junction to case)
Test Conditions
Still Air, soldered on a
3 × 4.5 inch, four-layer
printed circuit board
300-Mil Wide
SOJ
57.61
40.53
400-Mil Wide
SOJ
56.29
38.14
TSOP I
50.72
16.21
Unit
°C/W
°C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
[6]
ALL INPUT PULSES
90%
10%
90%
10%
Z = 50
OUTPUT
50
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
1.5 V
3.0 V
30 pF*
GND
Rise Time:
3
ns
(a)
(b)
Fall Time:
3
ns
High-Z characteristics:
5V
OUTPUT
INCLUDING
JIG AND
SCOPE
5 pF
R2
255
R1 480
(c)
Notes
5. Tested initially and after any design or process changes that may affect these parameters.
6. AC characteristics (except High-Z) are tested using the load conditions shown in
Figure 3
(a). High-Z characteristics are tested for all speeds using the test load shown
in
Figure 3
(c).
Document Number: 38-05468 Rev. *J
Page 5 of 16
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