XC61C
Series
Low Voltage Detectors (V
DF
= 0.8V½1.5V)
Standard Voltage Detectors (V
DF
1.6V½6.0V)
ETR0201_015a
■GENERAL
DESCRIPTION
The XC61C series are highly precise, low power consumption voltage detectors, manufactured using CMOS and laser
trimming technologies.
Detect voltage is extremely accurate with minimal temperature drift.
Both CMOS and N-ch open drain output configurations are available.
■APPLICATIONS
●Microprocessor
reset circuitry
●Memory
battery back-up circuits
●Power-on
reset circuits
●Power
failure detection
●System
battery life and charge voltage monitors
■FEATURES
: ± 2%
: ± 1%(Standard Voltage VD: 2.6V~5.1V)
Low Power Consumption
: 0.7μA (TYP.) [V
IN
=1.5V]
Detect Voltage Range
: 0.8V ~ 6.0V in 0.1V increments
Operating Voltage Range
: 0.7V ~ 6.0V (Low Voltage)
0.7V½10.0V (Standard Voltage)
Detect Voltage Temperature Characteristics
:
±100ppm/℃
(TYP.)
Output Configuration
: N-ch open drain or CMOS
Packages
: SSOT-24
SOT-23
SOT-89
TO-92
Environmentally Friendly
: EU RoHS Compliant, Pb Free
Highly Accurate
■TYPICAL
APPLICATION CIRCUITS
■TYPICAL
PERFORMANCE CHARACTERISTICS
1/18
XC61C
Series
■PIN
CONFIGURATION
TO-92
(SIDE VIEW)
■PIN
ASSIGNMENT
PIN NUMBER
SSOT-24
2
4
1
3
SOT-23
3
2
1
-
SOT-89
2
3
1
-
TO-92
2
3
1
-
PIN NAME
V
IN
V
SS
V
OUT
NC
FUNCTIONS
Supply Voltage Input
Ground
Output
No Connection
■PRODUCT
CLASSIFICATION
●Ordering
Information
XC61C①②③④⑤⑥⑦-⑧
(
*1
)
DESIGNATOR
①
②③
④
⑤
ITEM
Output Configuration
Detect Voltage
Output Delay
Detect Accuracy
SYMBOL
C
N
08 ~ 60
0
1
2
NR
NR-G
MR
MR-G
PR
PR-G
TH
TH-G
TB
TB-G
CMOS output
N-ch open drain output
e.g.0.9V
→ ②0, ③9
e.g.1.5V
→ ②1, ③5
No delay
Within
±1%
(V
DF(T)
=2.6V~5.1V)
Within
±2%
SSOT-24 (3,000/Reel)
SSOT-24 (3,000/Reel)
SOT-23 (3,000/Reel)
SOT-23 (3,000/Reel)
SOT-89 (1,000/Reel)
SOT-89 (1,000/Reel)
TO-92 Taping Type: Paper type (2,000/Tape)
TO-92 Taping Type: Paper type (2,000/Tape)
TO-92 Taping Type: Bag (500/Bag)
TO-92 Taping Type: Bag (500/Bag)
DESCRIPTION
⑥⑦-⑧
(*1)
Packages (Order Unit)
(*1)
The “-G” suffix denotes Halogen and Antimony free as well as being fully RoHS compliant.
2/18
XC61C
Series
■BLOCK
DIAGRAMS
(1) CMOS Output
(2) N-ch Open Drain Output
■ABSOLUTE
MAXIMUM RATINGS
Ta = 25
O
C
PARAMETER
Input Voltage
Output Current
CMOS
Output Voltage
N-ch Open Drain Output *1
N-ch Open Drain Output *2
SSOT-24
Power Dissipation
SOT-23
SOT-89
TO-92
Operating Ambient Temperature
Storage Temperature
Pd
V
OUT
*1
*2
SYMBOL
V
IN
I
OUT
RATINGS
V
SS
-0.3 ~ 9.0
V
SS
-0.3 ~ 12.0
50
V
SS
-0.3 ~ V
IN
+0.3
V
SS
-0.3 ~ 9.0
V
SS
-0.3 ~ 12.0
150
150
500
300
-40½+85
-55½+125
mW
V
UNITS
V
mA
Topr
Tstg
℃
℃
*1: Low voltage: V
DF(T)
=0.8V~1.5V
*2: Standard voltage: V
DF(T)
=1.6V~6.0V
3/18
XC61C
Series
■ELECTRICAL
CHARACTERISTICS
V
DF (T)
= 0.8V to 6.0V ± 2%
V
DF (T)
= 2.6V to 5.1V ± 1%
PARAMETER
Detect Voltage
SYMBOL
V
DF
CONDITIONS
V
DF(T)
=0.8V~1.5V *1
V
DF(T)
=1.6V~6.0V *2
V
DF(T)
=2.6V~5.1V *2
Hysteresis Range
V
HYS
V
IN
= 1.5V
V
IN
= 2.0V
V
IN
= 3.0V
V
IN
= 4.0V
V
IN
= 5.0V
V
DF(T)
= 0.8V to 1.5V
V
DF(T)
= 1.6V to 6.0V
N-ch V
DS
= 0.5V
CMOS, P-ch V
DS
= 2.1V
I
OUT
Output Current *2
N-ch V
DS
= 0.5V
V
IN
= 0.7V
V
IN
= 1.0V
V
IN
= 6.0V
V
IN
= 1.0V
V
IN
= 2.0V
V
IN
= 3.0V
V
IN
= 4.0V
V
IN
= 5.0V
V
IN
= 8.0V
MIN.
V
DF(T)
x 0.98
V
DF(T)
x 0.99
V
DF
x 0.02
-
-
-
-
-
0.7
0.7
0.10
0.85
-
1.0
3.0
5.0
6.0
7.0
-
-
*1
*2
Ta=25℃
TYP.
V
DF(T)
V
DF(T)
V
DF
x 0.05
0.7
0.8
0.9
1.0
1.1
-
-
0.80
2.70
-7.5
2.2
7.7
10.1
11.5
13.0
-10.0
-10
MAX.
V
DF(T)
x 1.02
V
DF(T)
x 1.01
V
DF
x 0.08
2.3
2.7
3.0
3.2
3.6
6.0
10.0
-
-
-1.5
-
-
-
-
-
-2.0
-
nA
V
IN
=6.0V, V
OUT
=6.0V
V
IN
=10.0V, V
OUT
=10.0V
UNITS
CIRCUITS
V
V
V
1
1
1
Supply Current
I
SS
μA
2
Operating Voltage *1
Operating Voltage *2
Output Current *1
V
IN
V
1
3
4
mA
3
CMOS, P-ch V
DS
= 2.1V
CMOS
Output
(Pch)
Leakage
I
LEAK
Current
N-ch
Open
Drain
Temperature
ΔV
DF
/
Characteristics
(ΔTopr½V
DF
)
Delay Time
t
DLY
(V
DR
→V
OUT
inversion)
NOTE:
*1: Low Voltage: V
DF(T)
=0.8V~1.5V
*2: Standard Voltage: V
DF(T)
=1.6V~6.0V
V
DF (T)
: Nominal detect voltage
Release Voltage: V
DR
= V
DF
+ V
HYS
V
IN
=V
DF
x0.9, V
OUT
=0V
4
3
-
-
-
10
±100
0.03
100
-
0.20
ppm/
℃
ms
1
5
-40℃
≦
Topr
≦
85℃
Inverts from V
DR
to V
OUT
4/18
XC61C
Series
■OPERATIONAL
EXPLANATION
(Especially prepared for CMOS output products)
①
When input voltage (V
IN
) is higher than detect voltage (V
DF), o
utput voltage (V
OUT
) will be equal to VIN.
(A condition of high impedance exists with N-ch open drain output configurations.)
②
When input voltage (V
IN
) falls below detect voltage (V
DF
), output voltage (V
OUT
) will be equal to the ground voltage (V
SS
)
level.
③
When input voltage (V
IN
) falls to a level below that of the minimum operating voltage (V
MIN
), output will become
unstable. (As for the N-ch open drain product of XC61CN, the pull-up voltage goes out at the output voltage.)
④
When input voltage (V
IN
) rises above the ground voltage (V
SS
) level, output will be unstable at levels below the
minimum operating voltage (V
MIN
). Between the V
MIN
and detect release voltage (V
DR
) levels, the ground voltage (V
SS
)
level will be maintained.
⑤
When input voltage (V
IN
) rises above detect release voltage (V
DR
), output voltage (V
OUT
) will be equal to V
IN
.
(A condition of high impedance exists with N-ch open drain output configurations.)
⑥
The difference between V
DR
and V
DF
represents the hysteresis range.
●Timing
Chart
5/18
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