MGA-16516
Low Noise, High Linearity Match Pair Low Noise Amplifier
Data Sheet
Description
Avago Technologies’ MGA-16516 is an economical, easy-
to-use GaAs MMIC match pair Low Noise Amplifier (LNA).
The LNA has low noise and high linearity achieved through
the use of Avago Technologies’ proprietary 0.25um GaAs
Enhancement-mode pHEMT process. It is housed in a
miniature 4.0 x 4.0 x 0.85mm
3
16-pin Quad-Flat-Non-Lead
(QFN) package. The compact footprint and low profile
coupled with low noise, high gain and high linearity make
the MGA-16516 an ideal choice as a low noise amplifier for
cellular infrastructure for GSM and CDMA. This device is
applicable to both Single and Balance mode. It is designed
for optimum use from 500MHz to 1.7GHz. For optimum
performance at higher frequency from 1.7GHz to 2.7GHz,
the MGA-17516 is recommended. Both MGA-16516 and
MGA-17516 share the same package and pinout.
Features
x
4.0 x 4.0 x 0.85 mm
3
16-lead QFN
x
Low noise figure
x
High linearity performance
x
GaAs E-pHEMT Technology
[1]
x
Low cost small package size: 4.0x4.0x0.85 mm
3
x
Excellent uniformity in product specifications
x
Tape-and-Reel packaging option available
Specifications
850MHz; 5V, 50mA (typ) per section
x
17.7 dB Gain
x
0.4 dB Noise Figure
x
11.8 dBm Input IP3
x
18.3 dBm Output Power at 1dB gain compression
Package Marking
Pin 13
Pin 14
Pin 16
Pin 16
Applications
Pin 1
Pin 2
Pin 3
Pin 4
16516
YYWW
XXX
Pin 12
Pin 11
Pin 10
Pin 9
x
Low noise amplifier for cellular infrastructure for GSM
and CDMA.
x
Other ultra low noise application.
GND
TOP VIEW
BOTTOM VIEW
Note:
Package marking provides orientation and identification
“16516” = Device Code
“YYWW“ = Year and Work Week
“XXXX” = Last 4 digit of Device Lot Number
Attention: Observe precautions for
handling electrostatic sensitive devices.
ESD Machine Model = 60 V
ESD Human Body Model = 350 V
Refer to Avago Application Note A004R:
Electrostatic Discharge, Damage and Control.
Pin 8
Pin 7
Pin 6
Pin 5
Pin Configuration
[4]
[3]
[2]
[1]
Pin
[16]
[15]
[14]
[13]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Use
Not Used
Not Used
Not Used
Not Used
RFin1
Not Used
Not Used
RFin2
Not Used
Not Used
Not Used
Not Used
RFout2
Not Used
Not Used
RFout1
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
Simplified Schematic
Vgg1
Ca7
Ca5
Vdd1
Ca11
Ca9
Ra1
L1
[4]
[3]
[2]
Ra4
Ra7
[1]
[16]
[15]
[14]
[13]
L2
RFin a
RFin b
C1
C3
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
C2
C4
RFout a
RFout b
L3
Cb5
Cb7
Rb1
Vgg2
Rb7
L4
Rb4 Cb9
Vdd2
Cb11
Note:
x
Enhancement mode technology employs positive gate voltage,
thereby eliminating the need of negative gate voltage associated
with conventional depletion mode devices.
2
Absolute Maximum Rating
[2]
T
A
= 25°C
Symbol
V
dd
V
gg
P
in,max
I
dd
P
diss
T
j
T
STG
Parameter
Device Voltage, RF output to ground
Gate Voltage
CW RF Input Power
(Vdd = 5.0, Id=50mA)
Device Current,
RFout to ground per channel
Total Power Dissipation
[4]
Junction Temperature
Storage Temperature
Units
V
V
dBm
mA
W
°C
°C
Absolute Max.
5.5
1
15
100
1
150
-65 to 150
Thermal Resistance
[3]
(V
dd
= 5.0V, I
dd
= 50mA per channel),
T
jc
= 49.4°C/W per channel
Notes:
2. Operation of this device in excess of any of
these limits may cause permanent damage.
3. Thermal resistance measured using Infra-Red
Measurement Technique with both channels
turned on hence I
dd_total
=100mA.
4. Power dissipation with both channels turned
on. Board temperature T
B
is 25°C. Derate at
20mW/°C for T
B
>100°C.
Electrical Specifications
[7-10]
RF performance at T
A
= 25°C, V
dd
5V, I
dd
= 50mA, 850MHz and 900MHz given for each RF channel, measured on demo
board in Figure 5 with component list in Table1 for 850 MHz matching.
Symbol
Vgg
Gain
Parameter and Test Condition
Operational Gate Voltage, I
dd
= 50mA
Gain
Frequency
850
900
Units
V
dB
dB
dBm
dBm
dB
dB
dBm
dBm
dB
dB
dB
dB
dB
dB
dB
dB
Min.
0.38
Typ.
0.48
17.7
Max.
0.63
15.8
17.4
11.8
18.8
IIP3
[8]
Output Third Order Intercept Point
850
900
10.5
12.4
0.40
0.41
18.3
19.3
8.9
7.0
3.3
4.7
29.9
29.5
45
45
0.70
NF
[9]
Noise Figure
850
900
OP1dB
Output Power at 1dB Gain Compression
850
900
IRL
Input Return Loss, 50: source
850
900
ORL
Output Return Loss, 50: load
850
900
REV ISOL
Reverse Isolation
850
900
ISOL
1-2
Isolation between RFin1 and RFin2
850
900
Notes:
7. Measurements at 850 MHz and 900 MHz are obtained using demo board described in Figure 5.
8. IIP3 test condition:
a. F
RF1
= 850 MHz, F
RF2
= 851 MHz with input power of -15dBm per tone.
b. F
RF1
= 900 MHz, F
RF2
= 901MHz with input power of -15dBm per tone.
9. For NF data, board losses of the input have not been de-embedded.
10. Use proper bias, heatsink and derating to ensure maximum channel temperature is not exceeded. See absolute maximum ratings and application
note for more details.
3
Product Consistency Distribution Charts
Mean : 0.483
Min : 0.38
Max : 0.63
Mean : 0.41
Max : 0.70
Figure 1. Vgg @ 900MHz, 5V, 50mA
Mean = 0.48
Figure 2. Noise Figure @ 900MHz, 5V, 50mA
Mean = 0.41
Mean : 12.4
Min : 10.5
Mean : 17.4
Min : 15.8
Max : 18.8
Figure 3. IIP3 @ 900MHz, 5V, 50mA
Mean = 12.4
Figure 4. Gain @ 900MHz, 5V, 50mA
Mean = 17.4
Notes:
1. Distribution data samples size is 500 samples taken from 4 different wafers. Future wafers allocated to this product may have nominal values
anywhere between the upper and lower limits. Circuit losses have not been de-embedded from actual measurement.
4
Demo Board Layout
– Recommended PCB material is 10 mils Rogers RO4350
with a total thickness 62 mils
– Suggested component values may vary according to
layout and PCB material.
Figure 5. Demo Board Layout Diagram
Demo Board Schematic
Vgg1
Vdd1
Table 1. Component list for 850 MHz matching.
Part
Size
0402
0402
0402
0402
0402
0402
0402
0402
0402
0805
0805
Value
15pF(Murata)
3.3pF(Murata)
30nH(Coilcraft)
22nH(Toko)
110Ohm(ROhm)
12pF(Murata)
6pF(Murata)
56Ohm(ROhm)
9.1Ohm(Rohm)
4.7uF(Murata)
4.7uF(Murata)
Detail Part Number
GJM1555C1H150JB01D
GJM1555C1H3R3CB01D
0402CS-30NXJLU
LL1005-FHL22NJ
MCR01MZCJ111
GJM1555C1H120JB01D
GJM1555C1H6R0CB01D
MCR01MZSJ560
MCR01MZSJ9R1
GRM21BR60J475KA11L
GRM21BR60J475KA11L
Ca7
Ca5
Ca11
Ra1
Ra4
Ca9
L2
C2
[16]
[15]
[14]
[13]
[9]
[10]
[11]
[12]
C1 , C3
C2, C4
L1, L3
L2, L4
Ra7, Rb7
L1
Ra7
RFin a
C1
[5]
[6]
[7]
[8]
[4]
[3]
[2]
[1]
RFout a
Ca5, Cb5
Ca9, Cb9
RFin b
C3
C4
RFout b
Ra1, Rb1
Ra4, Rb4
Ca7, Cb7
Ca11, Cb11
L3
Rb7
L4
Cb5
Cb7
Rb1
Rb4
Cb9
Cb11
Vgg2
Vdd2
Figure 6. Demo Board Schematic Diagram
5
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