CY7C1081DV33
64-Mbit (4 M × 16) Static RAM
Features
■
Functional Description
The CY7C1081DV33 is a high-performance CMOS static RAM
organized as 4,194,304 words by 16 bits.
To write to the device, take Chip Enables (CE
1
LOW and CE
2
HIGH) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
0
through I/O
7
) is
written into the location specified on the address pins (A
0
through
A
21
). If Byte High Enable (BHE) is LOW, then data from I/O pins
(I/O
8
through I/O
15
) is written into the location specified on the
address pins (A
0
through A
21
).
To read from the device, take Chip Enables (CE
1
LOW and CE
2
HIGH) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins appears
on I/O
0
to I/O
7
. If Byte High Enable (BHE) is LOW, then data from
memory appears on I/O
8
to I/O
15
. See the
Truth Table on page
9
for a complete description of read and write modes.
The input and output pins (I/O
0
through I/O
15
) are placed in a
high impedance state when the device is deselected (CE
1
HIGH
or CE
2
LOW), the outputs are disabled (OE HIGH), both byte
high enable and byte low enable are disabled (BHE, BLE HIGH),
or during a write operation (CE
1
LOW, CE
2
HIGH, and WE
LOW).
High speed
❐
t
AA
= 12 ns
Low active power
❐
I
CC
= 300 mA at 12 ns
Low complementary metal oxide semiconductor (CMOS)
standby power
❐
I
SB2
= 100 mA
Operating voltages of 3.3 ± 0.3 V
2.0-V data retention
Automatic power-down when deselected
Transistor-transistor logic (TTL)-compatible inputs and outputs
Easy memory expansion with CE
1
and CE
2
features
Available in Pb-free 48-ball fine ball grid array (FBGA) package
■
■
■
■
■
■
■
■
Logic Block Diagram
DATA
IN
DRIVERS
ROW DECODER
4M × 16
SENSE AMPS
A
(10:0)
RAM ARRAY
I/O
0
–I/O
7
I/O
8
–I/O
15
COLUMN DECODER
BHE
WE
OE
BLE
A
(21:11)
CE
2
CE
1
Cypress Semiconductor Corporation
Document #: 001-53992 Rev. *D
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised August 22, 2012
CY7C1081DV33
Contents
Selection Guide ................................................................ 3
Pin Configuration ............................................................. 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
DC Electrical Characteristics .......................................... 4
Capacitance ...................................................................... 4
Thermal Resistance .......................................................... 4
Data Retention Characteristics ....................................... 5
AC Switching Characteristics ......................................... 6
Switching Waveforms ...................................................... 7
Truth Table ........................................................................ 9
Ordering Information ...................................................... 10
Ordering Code Definition ........................................... 10
Package Diagram ............................................................ 11
Acronyms ........................................................................ 11
Document Conventions ................................................. 11
Units of Measure ....................................................... 11
Document History Page ................................................. 12
Sales, Solutions, and Legal Information ...................... 12
Worldwide Sales and Design Support ....................... 12
Products .................................................................... 12
PSoC Solutions ......................................................... 12
Document #: 001-53992 Rev. *D
Page 2 of 12
CY7C1081DV33
Selection Guide
Description
Maximum access time
Maximum operating current
Maximum CMOS standby current
–12
12
300
100
Unit
ns
mA
mA
Pin Configuration
Figure 1. 48-Ball FBGA (Top View)
1
BLE
I/O
8
I/O
9
V
SS
V
CC
2
OE
BHE
I/O
10
I/O
11
I/O
12
3
A
0
A
3
A
5
A
17
A
21
4
A
1
A
4
A
6
A
7
A
16
A
15
A
13
A
10
5
A
2
CE
1
I/O
1
I/O
3
I/O
4
I/O
5
WE
A
11
6
CE
2
I/O
0
I/O
2
V
CC
V
SS
I/O
6
I/O
7
A
19
A
B
C
D
E
F
G
H
I/O
14
I/O
13
A
14
I/O
15
A
18
A
20
A
8
A
12
A
9
Document #: 001-53992 Rev. *D
Page 3 of 12
CY7C1081DV33
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –65
C
to +150
C
Ambient temperature with
power applied ........................................... –55
C
to +125
C
Supply voltage on V
CC
relative to GND
[1]
....–0.5 V to +4.6 V
DC voltage applied to outputs
in high-Z state
[1]
................................... –0.5 V to V
CC
+ 0.5 V
DC input voltage
[1]
............................... –0.5 V to V
CC
+ 0.5 V
Current into outputs (LOW) ......................................... 20 mA
Static discharge voltage............. ...............................>2001 V
(MIL-STD-883, Method 3015)
Latch-up current ...................................................... >140 mA
Operating Range
Range
Industrial
Ambient
Temperature
–40 °C to +85 °C
V
CC
3.3 V
0.3 V
Speed
12 ns
DC Electrical Characteristics
Over the Operating Range
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
I
SB2
Description
Output HIGH voltage
Output LOW voltage
Input HIGH voltage
Input LOW voltage
[1]
Input leakage current
Output leakage current
V
CC
operating supply current
Automatic CE power-down
current – TTL inputs
Automatic CE power-down
current – CMOS inputs
GND < V
IN
< V
CC
GND < V
OUT
< V
CC
, Output Disabled
V
CC
= Max, f = f
max
= 1/t
RC,
I
OUT
= 0 mA CMOS levels
Max V
CC
, CE
1
> V
IH
, CE
2
< V
IL
,
V
IN
> V
IH
or V
IN
< V
IL
, f = f
max
Max V
CC
, CE
1
> V
CC
– 0.3 V, CE
2
< 0.3 V,
V
IN
> V
CC
– 0.3 V, or V
IN
< 0.3 V, f = 0,
Test Conditions
V
CC
= Min, I
OH
= –4.0 mA
V
CC
= Min, I
OL
= 8.0 mA
–12
Min
2.4
–
2.0
–0.3
–1
–1
–
–
–
Max
–
0.4
V
CC
+ 0.3
0.8
+1
+1
300
120
100
Unit
V
V
V
V
A
A
mA
mA
mA
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
C
IN
C
OUT
Description
Input capacitance
I/O capacitance
Test Conditions
T
A
= 25
C,
f = 1 MHz, V
CC
= 3.3 V
Max
32
40
Unit
pF
pF
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
JA
JC
Description
Thermal resistance
(junction to ambient)
Thermal resistance
(junction to case)
Test Conditions
Still air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
FBGA
55
23.04
Unit
C/W
C/W
Note
1. V
IL
(min) = –2.0 V and V
IH
(max) = V
CC
+ 2 V for pulse durations of less than 20 ns.
Document #: 001-53992 Rev. *D
Page 4 of 12
CY7C1081DV33
Figure 2. AC Test Loads and Waveforms
[2]
HIGH-Z CHARACTERISTICS:
R1 317
3.3 V
OUTPUT
5 pF*
INCLUDING
JIG AND
SCOPE
(b)
ALL INPUT PULSES
3.0 V
GND
90%
10%
90%
10%
50
OUTPUT
Z
0
= 50
(a)
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
V
TH
= 1.5 V
30 pF*
R2
351
RISE TIME:
> 1 V/ns
(c)
FALL TIME:
> 1 V/ns
Data Retention Characteristics
Over the Operating Range
Parameter
V
DR
I
CCDR
t
CDR[3]
t
R[4]
Description
V
CC
for data retention
Data retention current
Chip deselect to data
retention time
Operation recovery time
V
CC
= 2 V, CE
1
> V
CC
– 0.2 V, CE
2
< 0.2 V,
V
IN
> V
CC
– 0.2 V or V
IN
< 0.2 V
Conditions
Min
2
–
0
12
Typ
–
–
–
–
Max
–
100
–
–
Unit
V
mA
ns
ns
Figure 3. Data Retention Waveform
DATA RETENTION MODE
V
CC
3.0 V
t
CDR
CE
1
V
DR
> 2 V
3.0 V
t
R
CE
2
Notes
2. Valid SRAM operation does not occur until the power supplies reach the minimum operating V
DD
(3.0 V). 100
s
(t
power
) after reaching the minimum operating V
DD
,
normal SRAM operation begins to include reduction in V
DD
to the data retention (V
CCDR
, 2.0 V) voltage.
3. Tested initially and after any design or process changes that may affect these parameters.
4. Full device operation requires linear V
CC
ramp from V
DR
to V
CC
(min) > 50
s
or stable at V
CC
(min) > 50
s.
Document #: 001-53992 Rev. *D
Page 5 of 12
NXP MCU
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
