LH79524/LH79525 (A.0)
Preliminary Data Sheet
FEATURES
• Highly Integrated System-on-Chip
• High Performance: 76.205 MHz CPU Speed,
50.803 MHz maximum AHB clock (HCLK)
• 32-bit ARM720T™ RISC Core
– LH79524: 32-bit External Data Bus
– 208 CABGA package
– LH79525: 16-bit External Data Bus
– 176 LQFP package
• 8KB Cache with Write Back Buffer
• MMU (Windows CE™ Enabled)
• 16KB On-Chip SRAM
• Flexible, Programmable Memory Interface
– SDRAM Interface
– 512 MB External Address Space
– 32-bit External Data Bus (LH79524)
– 16-bit External Data Bus (LH79525)
– SRAM/Flash/ROM Interface
– 24-bit External Address Bus
– 32-bit External Data Bus (LH79524)
– 16-bit External Data Bus (LH79525)
• Multi-stream DMA Controller
– Four 32-bit Burst-Based Data Streams
• Clock and Power Management
– 32.768 kHz Oscillator for Real Time Clock
– 10 - 20 MHz Oscillator and On-chip PLL
– Active, Standby, Sleep, Stop1, and Stop2 Modes
– Externally-supplied Clock Options
• On-Chip Boot ROM
– Allows Booting from 8-, 16-, or 32-bit Devices
– NAND Flash Boot
• Low Power Modes
– Active Mode: 85 mA (MAX.)
– Standby Mode: 50 mA (MAX.)
– Sleep Mode: 3.8 mA (TYP.)
– Stop Mode 1: 420
μA
(TYP.)
– Stop Mode 2: 25
μA
(TYP.)
• USB Device
– Compliant with USB 2.0 Specifications (Full Speed)
– Four Endpoints
• Ethernet MAC, with MII and MDIO Interfaces
– IEEE 802.3 Compliant
– 10 and 100 Mbit/s Operation
• Analog-to-Digital Converter/Brownout Detector
– 10-bit ADC
– Pen Sense Interrupt
– Integrated Touch Screen Controller (TSC)
• I
2
C Module
Preliminary Data Sheet for Rev. A.0 Silicon
System-on-Chip
• Integrated Codec Interface Support Features (I
2
S)
• Watchdog Timer
• Vectored Interrupt Controller
– 16 Standard and 16 Vectored IRQ Interrupts
– Interrupts Individually Configurable as IRQ or FIQ
• Three UARTs
– 16-entry FIFOs for Rx and Tx
– IrDA SIR Support on all UARTs
• Three 16-bit Timers with PWM capability
• Real Time Clock
– 32-bit Up-counter with Programmable Load
– Programmable 32-bit Match Compare Register
• Programmable General Purpose I/O Signals
– LH79524: 108 available pins on 14 ports
– LH79525: 86 available pins on 12 ports
• Programmable Color LCD Controller
– 16 (LH79524) or 12 (LH79525) Bits-per-Pixel
– Up to 800 × 600 resolution
– STN, Color STN, HR-TFT, AD-TFT, TFT
– TFT: Supports 64 k (LH79524) or 4 k (LH79525)
Direct Colors or 256 Colors selected from a
Palette of 64 k Colors; 15 Shades of Gray
– Color STN: Supports 3,375 Direct Colors or 256
Colors Selected from a Palette of 3,375 Colors
• Synchronous Serial Port
– Supports Data Rates Up to 1.8452 Mbit/s
– Compatible with Common Interface Schemes
• JTAG Debug Interface and Boundary Scan
• 5 V Tolerant Digital Inputs (excludes oscillator pins)
– XTALIN and XTAL32IN pins are 1.8 V ± 10%
• On-Chip regulator allows single 3.3 V supply
DESCRIPTION
The LH79524/LH79525, powered by an ARM720T,
is a complete System-on-Chip with a high level of inte-
gration to satisfy a wide range of requirements and
applications. The SoC has a fully static design, power
management unit, and low voltage operation (1.8 V
Core, 3.3 V I/O). With the on-chip voltage regulator, a
single 3.3 V supply can be used as well. Robust periph-
erals and a low-power RISC core provide high perfor-
mance at a reasonable price.
This Data Sheet applies
to silicon Revision A.0 ONLY.
Devices containing lead-free solder formulations have different reflow
temperatures than leaded-solder formulations. When using both
solder formulations on the same PC board, consider the effect of
different reflow temperatures on the overall PCB assembly process.
ARM720T is a trademark of Advanced RISC Machines, LTD.
5/5/06
1
LH79524/LH79525
System-on-Chip
10 - 20 MHz
32.768 kHz
LH79524/LH79525
OSCILLATOR,
PLL(2), POWER
MANAGEMENT, and
RESET CONTROL
REAL TIME
CLOCK
ARM720T
CONDITIONED
EXTERNAL
INTERRUPTS
GENERAL
PURPOSE I/O
CACHE
VECTORED
INTERRUPT
CONTROLLER
I/O
CONFIGURATION
INTERNAL
INTERRUPTS
SYNCHRONOUS
SERIAL PORT
INTERNAL
16KB SRAM
ETHERNET
MAC
SSP - I
2
S
CONVERTER
(WITH CODEC
INTERFACE)
BOOT
ROM
BOOT
CONTROLLER
COUNTER/
TIMER (3)
4 CHANNEL
DMA
CONTROLLER
EXTERNAL
MEMORY
CONTROLLER
WATCHDOG
TIMER
USB
DEVICE
ADVANCED
PERIPHERAL
BUS BRIDGE
I
2
C
TEST
SUPPORT
COLOR
LCD
CONTROLLER
16550
UART (3) w/SIR
LINEAR
REGULATOR
ADVANCED
LCD
INTERFACE
ADVANCED
PERPHERAL
BUS (APB)
10 CHANNEL
10-BIT ADC
(WITH TSC and
BROWNOUT
DETECTOR)
ADVANCED HIGH
PERFORMANCE
BUS (AHB)
LH79525-1
Figure 1. LH79524/LH79525 Block Diagram
2
5/5/06
Preliminary Data Sheet for Rev. A.0 Silicon
System-on-Chip
LH79524/LH79525
SIGNAL DESCRIPTIONS
Table 1. LH79524 Pin Descriptions
CABGA
PIN
T12
R11
T11
P10
R10
T10
P9
R9
T9
T8
R8
P8
T7
R7
P7
T6
M15
N16
L13
M14
N15
P16
M13
N14
F14
G15
D13
E13
E14
G14
G16
H14
H15
H16
L16
L15
M16
L14
J15
J14
K16
K15
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
D0
D1
D2
D3
D4
D5
D6
D7
SDCLK
SDCKE
DQM0
DQM1
DQM2
DQM3
nDCS0
nDCS1
nRAS
nCAS
nCS0/PM0
nCS1/PM1
nCS2/PM2
nCS3/PM3
nBLE0/PM4
nBLE1/PM5
nBLE2/PM6
nBLE3/PM7
O
Static Memory Byte Lane Enable / Byte Write Enable; multiplexed with
GPIO Port M[7:4] (output only)
O
Static Memory Chip Select; multiplexed with GPIO Port M[3:0] (output only)
O
O
O
O
SDRAM Chip Select
SDRAM Chip Select
Row Address Strobe
Column Address Strobe
O
Data Mask Output to SDRAMs
O
O
SDRAM Clock
SDRAM Clock Enable
I/O
External Data Bus
O
External Address Bus
SIGNAL NAME
TYPE
DESCRIPTION
Preliminary Data Sheet for Rev. A.0 Silicon
5/5/06
3
LH79524/LH79525
System-on-Chip
Table 1. LH79524 Pin Descriptions (Cont’d)
CABGA
PIN
K14
J16
A16
A15
E2
F2
G2
H2
H3
F1
F3
E1
G3
G1
J3
N1
M2
L3
M1
L2
L1
K3
K2
R2
R1
P2
N3
M4
P1
N2
SIGNAL NAME
nOE
nWE
USBDN
USBDP
AN0/UL/X+
AN1/UR/X–
AN2/LL/Y+/PJ3
AN3/LR/Y–/PJ0
AN4/WIPER/PJ1
AN5/PJ5/INT5
AN6/PJ7/INT7
AN7/PJ6/INT6
AN8/PJ4
AN9/PJ2
CTCLK/INT4/BATCNTL
PA0/INT2/UARTRX2/
UARTIRRX2
PA1/INT3/UARTTX2/
UARTIRTX2
PA2/CTCAP0A/
CTCMP0A
PA3/CTCAP0B/
CTCMP0B
PA4/CTCAP1A/
CTCMP1A
PA5/CTCAP1B/
CTCMP1B
PA6/CTCAP2A/
CTCMP2A/SDA
PA7/CTCAP2B/
CTCMP2B/SCL
PB0/nDACK/
nUARTCTS0
PB1/DREQ/
nUARTRTS0
PB2/SSPFRM/I2SWS
PB3/SSPCLK/I2SCLK
PB4/SSPRX/I2SRXD/
UARTRX1/
UARTIRRX1
PB5/SSPTX/I2STXD/
UARTTX1/UARTIRTX1
PB6/INT0/UARTRX0/
UARTIRRX0
TYPE
O
O
I/O
I/O
I
I
I
I
I
I
I
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Static Memory Output Enable
Static Memory Write Enable
USB Data Negative (Differential Pair output, single ended and Differential pair input)
USB Data Positive (Differential Pair output, single ended and Differential pair input)
ADC Input 0, 4-wire touch screen Upper Left, 5-wire touch screen X+
ADC Input 1, 4-wire touch screen Upper Right, 5-wire touch screen X–
ADC Input 2, 4-wire touch screen Lower Left, 5-wire touch screen Y+; multiplexed
with GPIO Port J3 (input only)
ADC Input 3, 4-wire touch screen Upper Right, 5-wire touch screen Y–;
multiplexed with GPIO Port J0 (input only)
ADC Input 4, 5-wire touch screen Wiper input; multiplexed with GPIO Port J1
(input only)
ADC Input 5; multiplexed with GPIO Port J5 (input only) and External Interrupt 5
ADC Input 6; multiplexed with GPIO Port J7 (input only) and External Interrupt 7
ADC Input 7; multiplexed with GPIO Port J6 (input only) and External Interrupt 6
ADC Input 8; multiplexed with GPIO Port J4 (input only)
ADC Input 9; multiplexed with GPIO Port J2 (input only)
Timer[2:0] External Clock input; muxed with External Int 4 and Battery Control
General Purpose I/O Signal — Port A0; multiplexed with UART2 Received Serial
Data Input, UART2 Infrared Received Serial Data In, and External Interrupt 2
General Purpose I/O Signal — Port A1; multiplexed with UART2 Transmitted
Serial Data Output, UART2 Serial Transmit Data Out, and External Interrupt 3
General Purpose I/O Signal — Port A2; multiplexed with Counter/Timer 0
Capture A input and Counter/Timer 0 Compare A output
General Purpose I/O Signal — Port A3; multiplexed with Counter/Timer 0
Capture B input and Counter/Timer 0 Compare B output
General Purpose I/O Signal — Port A4; multiplexed with Counter/Timer 1
Capture A input and Counter/Timer 1 Compare A output
General Purpose I/O Signal — Port A5; multiplexed with Counter/Timer 1
Capture B input and Counter/Timer 1 Compare B output
General Purpose I/O Signal — Port A6; multiplexed with Counter/Timer 2
Capture A input, Counter/Timer 2 Compare A output, I
2
C Bus Data (open drain)
General Purpose I/O Signal — Port A7; multiplexed with Counter/Timer 2
Capture B input, Counter/Timer 2 Compare B output, I
2
C Bus Clock (open drain)
General Purpose I/O Signal — Port B0; multiplexed with DMA Acknowledge and
UART0 CTS
General Purpose I/O Signal — Port B1; multiplexed with DMA Request and
UART0 RTS
General Purpose I/O Signal — Port B2; multiplexed with SSP Serial Frame Output
and I
2
S Frame Output
General Purpose I/O Signal — Port B3; multiplexed with SSP Clock and I
2
S Clock
General Purpose I/O Signal — Port B4; multiplexed with SSP Data In, I
2
S Data In,
UART1 Serial Data In, and UART1 Infrared Data In
General Purpose I/O Signal — Port B5; multiplexed with SSP Data Out, I
2
S Data
Out, UART1 Data Out, and UART1 IR Data Out
General Purpose I/O Signal — Port B6; multiplexed with UART0 Infrared Received
Serial Data Input, UART0 Received Serial Data In, and External Interrupt 0
DESCRIPTION
4
5/5/06
Preliminary Data Sheet for Rev. A.0 Silicon
System-on-Chip
LH79524/LH79525
Table 1. LH79524 Pin Descriptions (Cont’d)
CABGA
PIN
M3
N7
R6
T5
P6
R5
T4
P5
R4
P15
P14
N13
T15
N12
T14
P12
T13
B12
D11
B13
C13
D12
B16
B15
D14
A8
A9
B9
C9
B10
A11
B11
A12
A5
B6
A6
C7
B7
SIGNAL NAME
PB7/INT1/UARTTX0/
UARTIRTX0
PC0/A16
PC1/A17
PC2/A18
PC3/A19
PC4/A20
PC5/A21
PC6/A22/nFWE
PC7/A23/nFRE
PD0/D8
PD1/D9
PD2/D10
PD3/D11
PD4/D12
PD5/D13
PD6/D14
PD7/D15
PE0/LCDLP/
LCDHRLP
PE1/LCDDCLK
PE2/LCDPS
PE3/LCDCLS
PE4/LCDDSPLEN/
LCDREV
PE5/LCDVDDEN
PE6/LCDVEEN/
LCDMOD
PE7/nWAIT/nDEOT
PF0/LCDVD6
PF1/LCDVD7
PF2/LCDVD8
PF3/LCDVD9
PF4/LCDVD10
PF5/LCDVD11
PF6/LCDEN/LCDSPL
PF7/LCDFP/LCDSPS
PG0/ETHERTXEN
PG1/ETHERTXCLK
PG2/LCDVD0
PG3/LCDVD1
PG4/LCDVD2
TYPE
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DESCRIPTION
General Purpose I/O Signal — Port B7; multiplexed with UART0 Infrared Transmit-
ted Serial Data Output, UART0 Serial Transmit Data Out, and External Interrupt 1.
General Purpose I/O Signal — Port C0; multiplexed with Address A16
General Purpose I/O Signal — Port C1; multiplexed with Address A17
General Purpose I/O Signal — Port C2; multiplexed with Address A18
General Purpose I/O Signal — Port C3; multiplexed with Address A19
General Purpose I/O Signal — Port C4; multiplexed with Address A20
General Purpose I/O Signal — Port C5; multiplexed with Address A21
General Purpose I/O Signal — Port C6; multiplexed with Address A22 and NAND
Flash Write Enable
General Purpose I/O Signal — Port C7; multiplexed with Address A23 and NAND
Flash Read Enable
General Purpose I/O Signal — Port D0; multiplexed with Data D8
General Purpose I/O Signal — Port D1; multiplexed with Data D9
General Purpose I/O Signal — Port D2; multiplexed with Data D10
General Purpose I/O Signal — Port D3; multiplexed with Data D11
General Purpose I/O Signal — Port D4; multiplexed with Data D12
General Purpose I/O Signal — Port D5; multiplexed with Data D13
General Purpose I/O Signal — Port D6; multiplexed with Data D14
General Purpose I/O Signal — Port D7; multiplexed with Data D15
General Purpose I/O Signals — Port E0; multiplexed with LCD Line Pulse and
AD-TFT/HR-TFT Line Pulse
General Purpose I/O Signals — Port E1; multiplexed with LCD Data Clock
General Purpose I/O Signals — Port E2; multiplexed with LCD Power Save
General Purpose I/O Signals — Port E3; multiplexed with LCD Row Driver Clock
General Purpose I/O Signals — Port E4; multiplexed with LCD Panel Power
Enable and LCD Reverse
General Purpose I/O Signals — Port E5; multiplexed with LCD VDD Enable
General Purpose I/O Signals — Port E6; multiplexed with LCD Analog Power
Enable and MOD
General Purpose I/O Signals — Port E7; multiplexed with nWAIT and DMA End of
Transfer
General Purpose I/O Signals — Port F0; multiplexed with LCD Video Data bit 6
General Purpose I/O Signals — Port F1; multiplexed with LCD Video Data bit 7
General Purpose I/O Signals — Port F2; multiplexed with LCD Video Data bit 8
General Purpose I/O Signals — Port F3; multiplexed with LCD Video Data bit 9
General Purpose I/O Signals — Port F4; multiplexed with LCD Video Data bit 10
General Purpose I/O Signals — Port F5; multiplexed with LCD Video Data bit 11
General Purpose I/O Signals — Port F6; multiplexed with LCD Start Pulse Left
General Purpose I/O Signals — Port F7; multiplexed with LCD Row Driver
Counter reset
General Purpose I/O Signals — Port G0; multiplexed with Ethernet TX Enable
General Purpose I/O Signals — Port G1; multiplexed with Ethernet TX Clock
General Purpose I/O Signals — Port G2; multiplexed with LCD Video Data bit 0
General Purpose I/O Signals — Port G3; multiplexed with LCD Video Data bit 1
General Purpose I/O Signals — Port G4; multiplexed with LCD Video Data bit 2
Preliminary Data Sheet for Rev. A.0 Silicon
5/5/06
5
嵌入式系统
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