MB9A110K Series
32-bit ARM
®
Cortex
®
-M3
FM3 Microcontroller
The MB9A110K Series are a highly integrated 32-bit microcontrollers dedicated for embedded controllers with high-performance and
low cost.
These series are based on the ARM
®
Cortex
®
-M3 Processor with on-chip Flash memory and SRAM, and has peripheral functions
such as Motor Control Timers, ADCs and Communication Interfaces (UART, CSIO, I
2
C, LIN).
The products which are described in this datasheet are placed into TYPE5 product categories in "FM3 Family Peripheral Manual".
Features
32-bit ARM
®
Cortex
®
-M3 Core
Processor version: r2p1
Up to 40 MHz Frequency Operation
Integrated Nested Vectored Interrupt Controller (NVIC): 1
NMI (non-maskable interrupt) and 48 peripheral interrupts
and 16 priority levels
Multi-function Serial Interface (Max 4 channels)
2 channels with 16-steps × 9-bits FIFO (ch.0, ch.1),
2 channels without FIFO (ch.3, ch.5)
Operation mode is selectable from the followings for each
channel.
(In ch.5, only UART and LIN are available.)
UART
CSIO
LIN
I
2
C
24-bit System timer (Sys Tick): System timer for OS task
management
On-chip Memories
[Flash memory]
This Series are based on two independent on-chip Flash
memories.
[UART]
Full-duplex double buffer
Selection with or without parity supported
Built-in dedicated baud rate generator
External clock available as a serial clock
Hardware Flow control: Automatically control the
transmission by CTS/RTS (only ch.4)
MainFlash
to 128 KB
Read cycle: 0 wait-cycle
Security function for code protection
Up
WorkFlash
KB
Read cycle: 0 wait-cycle
Security function is shared with code protection
32
Various error detect functions available (parity errors,
framing errors, and overrun errors)
[CSIO]
Full-duplex double buffer
Built-in dedicated baud rate generator
Overrun error detect function available
[SRAM]
This Series contain a total of up to 16 KB on-chip SRAM. This
is composed of two independent SRAM (SRAM0, SRAM1).
SRAM0 is connected to I-code bus and D-code bus of Cortex-
M3 core. SRAM1 is connected to System bus.
SRAM0: 8 KB
SRAM1: 8 KB
Cypress Semiconductor Corporation
Document Number: 002-05627 Rev. *B
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised March 22, 2017
MB9A110K Series
[LIN]
LIN protocol Rev.2.1 supported
Full-duplex double buffer
Master/Slave mode supported
LIN break field generate (can be changed 13 to 16-bit
length)
General Purpose I/O Port
This series can use its pins as General Purpose I/O ports
when they are not used for external bus or peripherals.
Moreover, the port relocate function is built in. It can set which
I/O port the peripheral function can be allocated.
Capable of pull-up control per pin
Capable of reading pin level directly
Built-in the port relocate function
Up 36 fast General Purpose I/O Ports
Some pin is 5 V tolerant I/O.
See "Pin Description" to confirm the corresponding pins.
LIN break delimiter generate (can be changed 1 to 4-bit
length)
Various error detect functions available (parity errors,
framing errors, and overrun errors)
[I C]
Standard mode (Max 100 kbps) / Fast-mode (Max 400 kbps)
supported
2
Multi-function Timer
The Multi-function timer is composed of the following blocks.
DMA Controller (4 channels)
DMA Controller has an independent bus for CPU, so CPU and
DMA Controller can process simultaneously.
16-bit free-run timer × 3 ch.
Input capture × 4 ch.
Output compare × 6 ch.
A/D activating compare × 3 ch.
Waveform generator × 3 ch.
16-bit PPG timer × 3 ch.
The following function can be used to achieve the motor
control.
8 independently configured and operated channels
Transfer can be started by software or request from the built-
in peripherals
Transfer address area: 32-bit (4 GB)
Transfer mode: Block transfer/Burst transfer/Demand
transfer
Transfer data type: byte/half-word/word
Transfer block count: 1 to 16
Number of transfers: 1 to 65536
A/D Converter (Max 8 channels)
[12-bit A/D Converter]
Successive Approximation Register type
Built-in 2 unit
Conversion time: 1.0 μs @ 5 V
Priority conversion available (priority at 2 levels)
Scanning conversion mode
Built-in FIFO for conversion data storage
(for SCAN conversion: 16 steps, for Priority conversion:
4 steps)
PWM signal output function
DC chopper waveform output function
Dead time function
Input capture function
A/D convertor activate function
DTIF (Motor emergency stop) interrupt function
Real-time clock (RTC)
The Real-time clock can count
Year/Month/Day/Hour/Minute/Second/A day of the week from
00 to 99.
Interrupt function with specifying date and time
(Year/Month/Day/Hour/Minute) is available. This function is
also available by specifying only Year, Month, Day, Hour or
Minute.
Timer interrupt function after set time or each set time.
Base Timer (Max 8 channels)
Operation mode is selectable from the followings for each
channel.
Capable of rewriting the time with continuing the time count.
Leap year automatic count is available.
16-bit PWM timer
16-bit PPG timer
16-/32-bit reload timer
16-/32-bit PWC timer
Document Number: 002-05627 Rev. *B
Page 2 of 81
MB9A110K Series
Quadrature Position/Revolution Counter (QPRC)
The Quadrature Position/Revolution Counter (QPRC) is used
to measure the position of the position encoder. Moreover, it is
possible to use up/down counter.
Clock and Reset
[Clocks]
Five clock sources (2 external oscillators, 2 internal CR
oscillator, and Main PLL) that are dynamically selectable.
The detection edge of the three external event input pins
AIN, BIN and ZIN is configurable.
Main Clock:
Sub Clock:
4 MHz to 48 MHz
32.768 kHz
16-bit position counter
16-bit revolution counter
Two 16-bit compare registers
Dual Timer (32/16-bit Down Counter)
The Dual Timer consists of two programmable 32/16-bit down
counters.
Operation mode is selectable from the followings for each
channel.
High-speed internal CR Clock: 4 MHz
Low-speed internal CR Clock: 100 kHz
Main PLL Clock
[Resets]
Reset requests from INITX pin
Power on reset
Software reset
Watchdog timers reset
Low-voltage detector reset
Clock supervisor reset
Free-running
Periodic (=Reload)
One-shot
Watch Counter
The Watch counter is used for wake up from Low Power
Consumption mode.
Interval timer: up to 64 s (Max) @ Sub Clock: 32.768 kHz
Clock Super Visor (CSV)
Clocks generated by internal CR oscillators are used to
supervise abnormality of the external clocks.
External Interrupt Controller Unit
Up to 6 external interrupt input pin
Include one non-maskable interrupt (NMI)
Watchdog Timer (2 channels)
A watchdog timer can generate interrupts or a reset when a
time-out value is reached.
This series consists of two different watchdogs, a "Hardware"
watchdog and a "Software" watchdog.
"Hardware" watchdog timer is clocked by low-speed internal
CR oscillator. Therefore, ”Hardware" watchdog is active in any
power saving mode except RTC and STOP and Deep stand-
by RTC and Deep stand-by STOP.
External OSC clock failure (clock stop) is detected, reset is
asserted.
External OSC frequency anomaly is detected, interrupt or
reset is asserted.
Low-Voltage Detector (LVD)
This Series include 2-stage monitoring of voltage on the VCC
pins. When the voltage falls below the voltage has been set,
Low-Voltage Detector generates an interrupt or reset.
LVD1: error reporting via interrupt
LVD2: auto-reset operation
Low Power Consumption Mode
Six Low Power Consumption modes supported.
CRC (Cyclic Redundancy Check) Accelerator
The CRC accelerator helps a verify data transmission or
storage integrity.
CCITT CRC16 and IEEE-802.3 CRC32 are supported.
SLEEP
TIMER
RTC
STOP
Deep stand-by RTC
Deep stand-by STOP
Debug
Serial Wire JTAG Debug Port (SWJ-DP)
CCITT CRC16 Generator Polynomial: 0x1021
IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7
Power Supply
Wide range voltage: VCC = 2.7 V to 5.5 V
Document Number: 002-05627 Rev. *B
Page 3 of 81
MB9A110K Series
Contents
1. Product Lineup .................................................................................................................................................................. 6
2. Packages ........................................................................................................................................................................... 7
3. Pin Assignment ................................................................................................................................................................. 8
4. List of Pin Functions....................................................................................................................................................... 11
5. I/O Circuit Type................................................................................................................................................................ 21
6. Handling Precautions ..................................................................................................................................................... 26
6.1
Precautions for Product Design ................................................................................................................................... 26
6.2
Precautions for Package Mounting .............................................................................................................................. 27
6.3
Precautions for Use Environment ................................................................................................................................ 28
7. Handling Devices ............................................................................................................................................................ 29
8. Block Diagram ................................................................................................................................................................. 31
9. Memory Size .................................................................................................................................................................... 31
10. Memory Map .................................................................................................................................................................... 32
11. Pin Status in Each CPU State ........................................................................................................................................ 35
12. Electrical Characteristics ............................................................................................................................................... 40
12.1 Absolute Maximum Ratings ......................................................................................................................................... 40
12.2 Recommended Operating Conditions.......................................................................................................................... 42
12.3 DC Characteristics....................................................................................................................................................... 43
12.3.1 Current Rating .............................................................................................................................................................. 43
12.3.2 Pin Characteristics ....................................................................................................................................................... 46
12.4 AC Characteristics ....................................................................................................................................................... 47
12.4.1 Main Clock Input Characteristics .................................................................................................................................. 47
12.4.2 Sub Clock Input Characteristics ................................................................................................................................... 48
12.4.3 Internal CR Oscillation Characteristics ......................................................................................................................... 48
12.4.4 Operating Conditions of Main PLL (In the case of using main clock for input of PLL) .................................................. 49
12.4.5 Operating Conditions of Main PLL (In the case of using high-speed internal CR)........................................................ 49
12.4.6 Reset Input Characteristics .......................................................................................................................................... 50
12.4.7 Power-on Reset Timing................................................................................................................................................ 50
12.4.8 Base Timer Input Timing .............................................................................................................................................. 51
12.4.9 CSIO/UART Timing ...................................................................................................................................................... 52
12.4.10 External Input Timing ................................................................................................................................................ 60
12.4.11 Quadrature Position/Revolution Counter timing ........................................................................................................ 61
12.4.12 I
2
C Timing ................................................................................................................................................................. 63
12.4.13 JTAG Timing ............................................................................................................................................................. 64
12.5 12-bit A/D Converter .................................................................................................................................................... 65
12.6 Low-Voltage Detection Characteristics ........................................................................................................................ 68
12.6.1 Low-Voltage Detection Reset ....................................................................................................................................... 68
12.6.2 Interrupt of Low-voltage Detection ............................................................................................................................... 68
12.7 MainFlash Memory Write/Erase Characteristics .......................................................................................................... 69
12.7.1 Write / Erase time......................................................................................................................................................... 69
12.7.2 Erase/write cycles and data hold time .......................................................................................................................... 69
12.8 WorkFlash Memory Write/Erase Characteristics ......................................................................................................... 69
12.8.1 Write / Erase time......................................................................................................................................................... 69
12.8.2 Erase/write cycles and data hold time .......................................................................................................................... 69
12.9 Return Time from Low-Power Consumption Mode ...................................................................................................... 70
12.9.1 Return Factor: Interrupt/WKUP .................................................................................................................................... 70
12.9.2 Return Factor: Reset .................................................................................................................................................... 72
Document Number: 002-05627 Rev. *B
Page 4 of 81
MB9A110K Series
13. Ordering Information ...................................................................................................................................................... 74
14. Package Dimensions ...................................................................................................................................................... 75
15. Major Changes ................................................................................................................................................................ 78
Document History ................................................................................................................................................................. 80
Sales, Solutions, and Legal Information ............................................................................................................................. 81
Document Number: 002-05627 Rev. *B
Page 5 of 81
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