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OX12PCI840: 产品描述Integrated Parallel Port and PCI interface; 文件大小548KB，共32页; 制造商ETC

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OX12PCI840概述

Integrated Parallel Port and PCI interface

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EATURE

•

IEEE1284 SPP/EPP/ECP parallel port

Single function target PCI controller, fully PCI 2.2 and

PCI Power Management 1.0 compliant

2 multi-purpose IO pins which can be configured as

interrupt input pins

•

OX12PCI840

Integrated Parallel Port

and PCI interface

Can be reconfigured using optional non-volatile

configuration memory (EEPROM)

5.0V operation

100 pin PQFP package

ESCRIPTION

The OX12PCI840 is a single chip solution for PCI-based

parallel expansion add-in cards. It is a single function PCI

device.

For legacy applications the PCI resources are arranged so

that the parallel port can be located at standard I/O

addresses.

The efficient 32-bit, 33MHz target- only PCI interface is

compliant with version 2.2 of the PCI Bus Specification and

version 1.0 of PCI Power Management Specification. For

full flexibility, all the default register values can be

overwritten using an optional Microwire

serial EEPROM.

The OX12PCI840 provides an IEEE1284 EPP/ECP parallel

port which fully supports the existing Centronics interface.

Oxford Semiconductor Ltd.

25 Milton Park, Abingdon, Oxon, OX14 4SH, UK

Tel: +44 (0)1235 824900

Fax: +44(0)1235 821141

Oxford Semiconductor 1999

OX12PCI840 1.2 – Dec 2001

Part No. OX12PCI840-PQC-A

OXFORD SEMICONDUCTOR LTD.

OX12PCI840

ONTENTS

4.1

4.2

4.2.1

4.3

4.3.1

4.4

4.4.1

4.4.2

4.4.3

4.4.4

4.4.5

4.5

4.6

4.6.1

PIN INFORMATION .....................................................................................................................4

PIN DESCRIPTIONS ....................................................................................................................5

CONFIGURATION & OPERATION ...............................................................................................8

PCI TARGET CONTROLLER .......................................................................................................9

OPERATION.......................................................................................................................................................................... 9

CONFIGURATION SPACE................................................................................................................................................... 9

PCI CONFIGURATION SPACE REGISTER MAP ......................................................................................................... 10

ACCESSING LOGICAL FUNCTIONS................................................................................................................................ 11

PCI ACCESS TO PARALLEL PORT .............................................................................................................................. 11

ACCESSING LOCAL CONFIGURATION REGISTERS .................................................................................................... 12

LOCAL CONFIGURATION AND CONTROL REGISTER ‘LCC’ (OFFSET 0X00) ......................................................... 12

MULTI-PURPOSE I/O CONFIGURATION REGISTER ‘MIC’ (OFFSET 0X04)............................................................. 13

LOCAL BUS TIMING PAR AMETER REGISTER 1 ‘LT1’ (OFFSET 0X08): ................................................................... 13

LOCAL BUS TIMING PAR AMETER/BAR SIZING REGISTER 2 ‘LT2’ (OFFSET 0X0C):............................................. 14

GLOB AL INTERRUPT STATUS AND CONTROL REGISTER ‘GIS’ (OFFSET 0X10) ................................................. 15

PCI INTERRUPTS ............................................................................................................................................................... 16

POWER MANAGEMENT.................................................................................................................................................... 17

POWER MANAGEMENT USING MIO............................................................................................................................ 17

5.1

OPERATION AND MODE SELECTION............................................................................................................................. 18

5.1.1

SPP MODE ...................................................................................................................................................................... 18

5.1.2

PS2 MODE ...................................................................................................................................................................... 18

5.1.3

EPP MODE ...................................................................................................................................................................... 18

5.1.4

ECP MODE ...................................................................................................................................................................... 18

5.2

PARALLEL PORT INTERRUPT ......................................................................................................................................... 18

5.3

REGISTER DESCRIPTION................................................................................................................................................. 19

5.3.1

PARALLEL PORT DATA REGISTER ‘PDR’................................................................................................................... 19

5.3.2

ECP FIFO ADDRESS / RLE ........................................................................................................................................... 19

5.3.3

DEVICE STATUS REGISTER ‘DSR’.............................................................................................................................. 19

5.3.4

DEVICE CONTROL REGISTER ‘DCR’ .......................................................................................................................... 20

5.3.5

EPP ADDRESS REGISTER ‘EPPA’ ............................................................................................................................... 20

5.3.6

EPP DATA REGISTERS ‘EPPD1-4’ ............................................................................................................................... 20

5.3.7

ECP DATA FIFO............................................................................................................................................................. 20

5.3.8

TEST FIFO...................................................................................................................................................................... 20

5.3.9

CONFIGURATION A REGISTER ................................................................................................................................... 20

5.3.10

CONFIGURATION B REGISTER ................................................................................................................................... 21

5.3.11

EXTENDED CONTROL REGISTER ‘ECR’ .................................................................................................................... 21

BI-DIRECTIONAL PARALLEL PORT..........................................................................................18

6.1

6.2

6.2.1

6.2.2

6.2.3

6.2.4

6.2.5

SERIAL EEPROM...................................................................................................................... 22

SPECIFICATION ................................................................................................................................................................. 22

EEPROM DATA ORGANISA

TION ..................................................................................................................................... 22

ZONE0: HEADER............................................................................................................................................................ 22

ZONE1: LOCAL CONFIGURATION REGISTERS ......................................................................................................... 23

ZONE2: IDENTIFICATION REGISTERS........................................................................................................................ 23

ZONE3: PCI CONFIGURATION REGISTERS ............................................................................................................... 23

ZONE4: FUNCTION ACCESS........................................................................................................................................ 25

OPERATING CONDITIONS ........................................................................................................26

Data Sheet Revision 1.2

Page 2

OX12PCI840

OX12PCI840概述

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