19-3488; Rev 2; 1/07
KIT
ATION
EVALU
BLE
AVAILA
Multichannel, True-Differential,
Serial, 14-Bit ADCs
General Description
Features
♦
8-Channel Single-Ended or 4-Channel Differential
Inputs (MAX1148/MAX1149)
♦
4-Channel Single-Ended or 2-Channel Differential
Inputs (MAX1146/MAX1147)
♦
Internal Multiplexer and T/H
♦
Single-Supply Operation
4.75V to 5.25V Supply (MAX1146/MAX1148)
2.7V to 3.6V Supply (MAX1147/MAX1149)
♦
Internal Reference
+4.096V (MAX1146/MAX1148)
+2.500V (MAX1147/MAX1149)
♦
116ksps Sampling Rate
♦
Low Power
1.1mA (116ksps)
120µA (10ksps)
12µA (1ksps)
300nA (Power-Down Mode)
♦
SPI-/QSPI-/MICROWIRE Compatible
♦
20-Pin TSSOP
MAX1146–MAX1149
The MAX1146–MAX1149 low-power, 14-bit, multichan-
nel, analog-to-digital converters (ADCs) feature an
internal track/hold (T/H), voltage reference, and clock.
The MAX1146/MAX1148 operate from a single +4.75V
to +5.25V supply, and the MAX1147/MAX1149 operate
from a single +2.7V to +3.6V supply. All analog inputs
are software configurable for unipolar/bipolar and sin-
gle-ended/differential operation.
The 4-wire serial interface connects directly to
SPI™/QSPI™/MICROWIRE™ devices without external
logic. The serial strobe output (SSTRB) allows conve-
nient connection to digital signal processors. The
MAX1146–MAX1149 use an internal clock or an exter-
nal serial-interface clock to perform successive-approx-
imation analog-to-digital conversions.
The MAX1146/MAX1148 include an internal +4.096V
reference, while the MAX1147/MAX1149 include an
internal +2.500V reference. All devices accept an exter-
nal reference from 1.5V to V
DD
.
The MAX1146–MAX1149 provide a hardware shutdown
and two software power-down modes. Using the soft-
ware power-down modes allows the devices to be pow-
ered down between conversions. When powered down,
accessing the serial interface automatically powers up
the devices. The quick turn-on time allows power-down
between all conversions. This technique reduces sup-
ply current to under 120µA for quick turn-on.
The MAX1146–MAX1149 are available in a 20-pin
TSSOP package.
Applications
Portable Data Logging
Data Acquisition
Medical Instruments
Battery-Powered Instruments
Process Control
SPI/QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
Pin Configurations appear at end of data sheet.
Ordering Information/Selector Guide
PART
MAX1146BCUP
MAX1146BEUP
MAX1147BCUP
MAX1147BEUP
MAX1148BCUP
MAX1148BEUP
MAX1149BCUP
MAX1149BEUP
TEMP
RANGE
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
PIN-
PACKAGE
20 TSSOP
20 TSSOP
20 TSSOP
20 TSSOP
20 TSSOP
20 TSSOP
20 TSSOP
20 TSSOP
INL
(LSB)
±2
±2
±2
±2
±2
±2
±2
±2
INPUT
CHANNELS
4
4
4
4
8
8
8
8
INTERNAL
REFERENCE (V)
+4.096
+4.096
+2.500
+2.500
+4.096
+4.096
+2.500
+2.500
PKG
CODE
U20-3
U20-3
U20-3
U20-3
U20-3
U20-3
U20-3
U20-3
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Multichannel, True-Differential,
Serial, 14-Bit ADCs
MAX1146–MAX1149
ABSOLUTE MAXIMUM RATINGS
V
DD
to AGND, DGND ............................................-0.3V to +6.0V
AGND to DGND.....................................................-0.3V to +0.3V
CH0–CH7, COM to AGND..........................-0.3V to (V
DD
+ 0.3V)
REF, REFADJ to AGND ..............................-0.3V to (V
DD
+ 0.3V)
Digital Inputs to DGND...............................-0.3V to (V
DD
+ 0.3V)
Digital Outputs to DGND ............................-0.3V to (V
DD
+ 0.3V)
Digital Output Sink Current .................................................25mA
Continuous Power Dissipation (T
A
= +70°C)
20 TSSOP (derate 10.9mW/°C above +70°C) .............879mW
Operating Temperature Ranges
MAX114_ BC_ _ ..................................................0°C to +70°C
MAX114_ BE_ _ ...............................................-40°C to +85°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
DD
= 5V (MAX1146/MAX1148), V
DD
= 3.3V (MAX1147/MAX1149),
SHDN
= V
DD
, V
COM
= 0, f
SCLK
= 2.1MHz, external clock (50%
duty cycle), 18 clocks/conversion (116ksps), V
REFADJ
= V
DD
, C
REF
= 2.2µF, external +4.096V reference at REF (MAX1146/
MAX1148), external 2.500V reference at REF (MAX1147/MAX1149), T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at
T
A
= +25°C.)
PARAMETER
DC ACCURACY (Note 1)
Resolution
Relative Accuracy (Note 2)
Differential Nonlinearity
Offset Error
Offset Temperature Coefficient
Gain Error
Gain Temperature Coefficient
Channel-to-Channel Offset
Matching
Channel-to-Channel Gain
Matching
(Note 3)
±0.8
±1
±1
0.3
±20
INL
DNL
No missing codes over temperature
-1.0
14
±0.7
±0.5
±2
+1.5
±10
Bits
LSB
LSB
LSB
ppm/°C
LSB
ppm/°C
LSB
LSB
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DYNAMIC SPECIFICATIONS (1kHz sine-wave input, 2.5VP-P, full-scale analog input, 116ksps, 2.1MHz external clock)
Signal-to-Noise Plus Distortion
Ratio
Total Harmonic Distortion
Spurious-Free Dynamic Range
Channel-to-Channel Crosstalk
Small-Signal Bandwidth
Full-Power Bandwidth
CONVERSION RATE
Conversion Time (Note 5)
SSBW
FPBW
SINAD
THD
SFDR
(Note 4)
-3dB point
SINAD > 68dB
External clock, 2.1MHz 15 SCLK cycles
Internal clock
7.2
6
8
Up to the 5th harmonic
84
77
81
-96
98
-85
3.0
2.0
-88
dB
dB
dB
dB
MHz
MHz
tCONV
µs
2
_______________________________________________________________________________________
Multichannel, True-Differential,
Serial, 14-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 5V (MAX1146/MAX1148), V
DD
= 3.3V (MAX1147/MAX1149),
SHDN
= V
DD
, V
COM
= 0, f
SCLK
= 2.1MHz, external clock (50%
duty cycle), 18 clocks/conversion (116ksps), V
REFADJ
= V
DD
, C
REF
= 2.2µF, external +4.096V reference at REF (MAX1146/
MAX1148), external 2.500V reference at REF (MAX1147/MAX1149), T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at
T
A
= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
Internal clock mode,
fSCLK = 2.1MHz
18 clocks/conversion
24 clocks/conversion
MIN
TYP
MAX
60.3
51.5
116.66
87.50
1.4
20
<50
External clock mode
Internal clock mode
0.1
0
2.1
Unipolar, COM = 0
Bipolar, COM = VREF / 2, single-ended
On/off-leakage current, VCH_ = 0 to VDD
±0.01
18
MAX1147/MAX1149, T
A
= +25°C
MAX1146/MAX1148, T
A
= +25°C
REF = DGND
MAX114_ BC _ _
MAX114_ BE _ _
0 to 0.2mA output load (Note 8)
2
0.01
1.250
±18
Pull REFADJ high to disable the internal
bandgap reference and reference buffer
MAX1147/MAX1149
MAX1146/MAX1148
V
DD
-
0.25V
2.000
3.277
±30
±40
2.0
2.480
4.076
2.500
4.096
2.520
4.116
20
±50
±60
0
VREF
±VREF / 2
±1
2.1
2.1
µs
ns
ps
MHz
MHz
ksps
UNITS
MAX1146–MAX1149
Throughput Rate
fSAMPLE
External clock mode, 18 clocks/conversion
fSCLK = 2.1MHz
24 clocks/conversion
T/H Acquisition Time
Aperture Delay
Aperture Jitter
Serial Clock Frequency
Internal Clock Frequency
ANALOG INPUTS (CH0–CH7, COM)
Input Voltage Range, Single-
Ended and Differential (Note 6)
Multiplexer Leakage Current
Input Capacitance
tACQ
tAD
tAJ
fSCLK
V
µA
pF
INTERNAL REFERENCE (C
REF
= 2.2µF, C
REFADJ
= 0.01µF)
REF Output Voltage
REF Short-Circuit Current
V
REF
Tempco (Note 7)
Load Regulation
Capacitive Bypass at REF
Capacitive Bypass at REFADJ
REFADJ Output Voltage
REFADJ Input Range
REFADJ Logic High
Reference Buffer Voltage Gain
V
REF
I
REFSC
V
mA
ppm/°C
mV
µF
µF
V
mV
V
V/V
_______________________________________________________________________________________
3
Multichannel, True-Differential,
Serial, 14-Bit ADCs
MAX1146–MAX1149
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 5V (MAX1146/MAX1148), V
DD
= 3.3V (MAX1147/MAX1149),
SHDN
= V
DD
, V
COM
= 0, f
SCLK
= 2.1MHz, external clock (50%
duty cycle), 18 clocks/conversion (116ksps), V
REFADJ
= V
DD
, C
REF
= 2.2µF, external +4.096V reference at REF (MAX1146/
MAX1148), external 2.500V reference at REF (MAX1147/MAX1149), T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at
T
A
= +25°C.)
PARAMETER
EXTERNAL REFERENCE AT REF
REF Input Voltage Range
REF Input Current
REF Input Resistance
DIGITAL INPUTS (DIN, SCLK,
CS, SHDN)
Input High Voltage
Input Low Voltage
Input Hysteresis
Input Leakage
Input Capacitance
DIGITAL OUTPUT (DOUT, SSTRB)
Output-Voltage Low
Output-Voltage High
Tri-State Leakage Current
Tri-State Output Capacitance
POWER REQUIREMENTS
Positive Supply Voltage
V
DD
MAX1147/MAX1149
MAX1146/MAX1148
Normal
operation, full-
scale input
Fast power-down
Shutdown Supply Current
(Note 8)
Power-Supply Rejection (Note 9)
PSR
Full power-down
SHDN
= DGND
External reference
External
reference
116ksps
10ksps
1ksps
2.7
4.75
1.1
0.12
0.012
1.9
120
0.3
0.3
±0.2
10
mV
µA
3.6
5.25
1.5
mA
V
V
OL
V
OH
I
L
C
OUT
I
SINK
= 2mA
I
SOURCE
= 2mA
CS
= V
DD
CS
= V
DD
10
V
DD
- 0.5
±10
0.4
V
V
µA
pF
V
IH
V
IL
V
HYST
I
IN
C
IN
10
0.2
±1
V
DD
< 3.6V
V
DD
> 3.6V
2.0
3.0
0.8
V
V
V
µA
pF
V
REF
I
REF
1.5
125
Shutdown
6
0.01
8
V
DD
+
50mV
450
10
V
µA
kΩ
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Supply Current (Note 8)
I
DD
Internal reference at
116ksps
2.4
mA
4
_______________________________________________________________________________________
Multichannel, True-Differential,
Serial, 14-Bit ADCs
TIMING CHARACTERISTICS
(V
DD
= 4.75V to 5.25V (MAX1146/MAX1148), V
DD
= 2.7V to 3.6V (MAX1147/MAX1149),
SHDN
= V
DD
, V
COM
= 0, f
SCLK
= 2.1MHz,
external clock (50% duty cycle), 18 clocks/conversion (116ksps), V
REFADJ
= V
DD
, C
REF
= 2.2µF, external +4.096V reference at REF
for the MAX1146/MAX1148, external 2.500V reference at REF for the MAX1147/MAX1149, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Typical values are at T
A
= +25°C.) (Figures 1, 2, and 3)
PARAMETER
DIN to SCLK Setup Time
DIN to SCLK Hold Time
SCLK Fall to Output Data Valid
CS
Fall to DOUT Enable
CS
Rise to DOUT Disable
SHDN
Rise
CS
Fall to SCLK Rise
Time
SHDN
Rise
CS
Fall to SCLK Rise
Hold Time
SCLK Clock Frequency
SCLK Pulse-Width High
SCLK Pulse-Width Low
CS
Fall to SSTRB Output Enable
CS
Rise to SSTRB Output Disable
SSTRB Rise to SCLK Rise
SCLK Fall to SSTRB Edge
CS
Pulse Width
SYMBOL
t
DS
t
DH
t
DOV
t
DOE
t
DOD
t
CSS
t
CSH
f
SCLK
t
CH
t
CL
t
STE
t
STD
t
SCK
t
SCST
t
CSW
100
External clock mode
Internal clock mode
Internal clock mode
Internal clock mode
External clock mode only
External clock mode only
Internal clock mode only
0
80
C
LOAD
= 50pF
C
LOAD
= 50pF
C
LOAD
= 50pF
50
50
0.1
0
100
100
120
120
2.1
2.1
CONDITIONS
MIN
50
0
10
80
120
120
TYP
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
MAX1146–MAX1149
Note 1:
Tested at V
DD
= 3.0V (MAX1147/MAX1149) or 5.0V(MAX1146/MAX1148); V
COM
= 0; unipolar single-ended input mode.
Note 2:
Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3:
Offset nulled. Measured with external reference.
Note 4:
“On” channel grounded; full-scale 1kHz sine wave applied to all “off” channels.
Note 5:
Conversion time defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle. (See
Figures 8–11.)
Note 6:
The common-mode range for the analog inputs is from AGND to V
DD
.
Note 7:
Digital inputs equal V
DD
or DGND.
Note 8:
External load should not change during conversion for specified accuracy.
Note 9:
Measured as (V
FS
x 3.6V) - (V
FS
x 2.7V) for the MAX1147/MAX1149 and (V
FS
x 5.25V) - (V
FS
x 4.75V) for the
MAX1146/MAX1148. V
DD
= 3.6V to 2.7V for MAX1147/MAX1149 and V
DD
= 5.25V to 4.75V for the MAX1146/MAX1148.
_______________________________________________________________________________________
5
stm32/stm8
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
