DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD161401
256-COLOR, 1/80-DUTY LCD CONTROLLER/DRIVER WITH ON-CHIP RAM
DESCRIPTION
The
µ
PD161401 is an LCD controller/driver with RAM and is capable of driving a full-dot LCD. It can display 256
colors on an RGB-STN color LCD. This LCD controller/driver can drive a full-dot LCD of up to 101
×
80 pixel with a
single chip.
FEATURES
•
LCD driver with on-chip display RAM
•
Logic power supply operation from +1.8 V to +3.6 V
•
Internal booster circuit: x 2 to x 7 selectable
•
Dot display RAM: (101 x 80) x 8 bits
•
8 (R, G)/4 (B) grayscales selectable from 17 levels
•
Full-dot output: 303 segment lines and 80 common lines
•
Serial interface (SI, SCL) or 8-/16-bit parallel data input (i80 or M68 system interface)
•
On-chip voltage divider resistor
•
Selectable bias value: 1/9 to 1/5
•
Selectable duty ratio: 1/80, 1/72 and 1/64 (main duty)
•
On-chip oscillator
ORDERING INFORMATION
Part Number
Package
Wafer/Chip (supports COF)
µ
PD161401W/P
Remark
Purchasing the above chip entail the exchange of documents such as a separate memorandum or product
quality, so please contact one of our sales representatives.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No.
S15726EJ2V0DS00 (2nd Edition)
Data Published June 2002 NS CP(K)
Printed in Japan
The mark
5
shows major revised points.
©
2001
µ
PD161401
CONTENT
1. BLOCK DIAGRAM ................................................................................................................................... 5
2. PIN CONFIGURATION (Pad Layout) ..................................................................................................... 6
3. PIN FUNCTIONS...................................................................................................................................... 12
3.1 Power Supply Pins...........................................................................................................................................12
3.2 Logic Circuit Pins ............................................................................................................................................13
3.3 Driver Pins ........................................................................................................................................................15
4. PIN I/O CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS.................................... 16
5. FUNCTIONAL DESCRIPTION................................................................................................................. 17
5.1 CPU Interface ....................................................................................................................................................17
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
Selecting interface type...........................................................................................................................17
Parallel interface .....................................................................................................................................17
Serial interface........................................................................................................................................19
Chip select ..............................................................................................................................................19
Accessing display data RAM and internal registers ................................................................................19
5.2 Display Data RAM ............................................................................................................................................21
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.2.6
5.2.7
Display data RAM ...................................................................................................................................21
X address circuit .....................................................................................................................................21
Y address circuit .....................................................................................................................................23
Column address circuit ...........................................................................................................................24
Common scan circuit ..............................................................................................................................25
Display data latch circuit .........................................................................................................................28
Arbitrary address area access (window access mode (WAS)) ...............................................................28
5.3 Screen Processing...........................................................................................................................................30
5.3.1
5.3.2
Blink/reverse display circuit.....................................................................................................................30
Example of setting blink area..................................................................................................................33
5.4 Oscillator ..........................................................................................................................................................33
5.5 Display Timing Generator ...............................................................................................................................35
5.6 Power Supply Circuit .......................................................................................................................................37
5.6.1
5.6.2
5.6.3
5.6.4
5.6.5
Power supply circuit ................................................................................................................................37
Booster circuit .........................................................................................................................................37
Voltage regulator circuit ..........................................................................................................................39
Level voltage control by operational amplifier .........................................................................................42
Application example of power supply circuit ...........................................................................................44
5.7 Driving LCD ......................................................................................................................................................48
5.7.1
2
Full-dot pulse modulation........................................................................................................................48
Data Sheet S15726EJ2V0DS
µ
PD161401
5.7.2
5.7.3
5.7.4
5.7.5
Grayscale palette....................................................................................................................................51
Setting of display size .............................................................................................................................52
Setting of LCD N-line inversion and M-line shift......................................................................................52
Reverse driving between frames ............................................................................................................54
5.8 Display Mode....................................................................................................................................................55
5.8.1
Selecting display mode ...........................................................................................................................55
5.8.2 Screen scrolling .......................................................................................................................................58
5.8.3 Scroll setting examples ............................................................................................................................59
5.9 Reset .................................................................................................................................................................61
6. COMMANDS ............................................................................................................................................ 63
6.1 Control Register 1 (R0)....................................................................................................................................64
6.2 Control Register 2 (R1)....................................................................................................................................65
6.3 Reset Command Register (R3) .......................................................................................................................66
6.4 X Address Register (R4) ..................................................................................................................................66
6.5 Y Address Register (R5) ..................................................................................................................................66
6.6 MIN.·X Address Register (R7) .........................................................................................................................67
6.7 MAX.·X Address Register (R8) ........................................................................................................................67
6.8 MIN.·Y Address Register (R9) .........................................................................................................................67
6.9 MAX.·Y Address Register (R10) ......................................................................................................................68
6.10 Display Memory Access Register (R12).......................................................................................................68
6.11 Main Duty Setting Register (R14) .................................................................................................................69
6.12 Main Duty N-line Inversion Register (R15)...................................................................................................69
6.13 Main Duty M-line Shift Register (R16) ..........................................................................................................70
6.14 Sub-duty Setting Register (R17) ...................................................................................................................71
6.15 Sub-duty N-line Inversion Register (R18) ....................................................................................................72
6.16 Sub-duty M-line Shift Register (R19)............................................................................................................73
6.17 COM Scanning Address Setting Register (R21)..........................................................................................74
6.18 Sub-duty Start Address Register (R22)........................................................................................................77
6.19 Scroll Fixed Area Position Register (R23) ...................................................................................................78
6.20 Scroll Fixed Area Width Register (R27) .......................................................................................................78
6.21 Scroll Step Number Register (R31) ..............................................................................................................79
6.22 Blink/Reverse Setting Register (R37)...........................................................................................................80
6.23 Complementary Color Blink X Address Register (R38) ..............................................................................80
6.24 Complementary Color Blink Start Line Address Register (R39)................................................................81
6.25 Complementary Color Blink End Line Address Register (R40) .................................................................81
6.26 Complementary Color Blink Data Memory Register (R41) .........................................................................82
6.27 Specified Color Blink X Address Register (R42) .........................................................................................82
6.28 Specified Color Blink Start Line Address Register (R43) ...........................................................................83
6.29 Specified Color Blink End Line Address Register (R44) ............................................................................83
6.30 Specified Color Blink Data Memory Register (R45) ....................................................................................84
6.31 Specified Color Setting Register (R46) ........................................................................................................84
Data Sheet S15726EJ2V0DS
3
µ
PD161401
6.32 Reverse X Address Register (R47) ...............................................................................................................84
6.33 Reverse Start Line Address Register (R48) .................................................................................................85
6.34 Reverse End Line Address Register (R49) ..................................................................................................85
6.35 Reverse Data Memory Access Register (R50).............................................................................................86
6.36 Power System Control Register 1 (R52) ......................................................................................................87
6.37 Power System Control Register 2 (R53) ......................................................................................................88
6.38 Power System Control Register 3 (R54) ......................................................................................................89
6.39 Power System Control Register 4 (R55) ......................................................................................................90
6.40 Power System Control Register 5 (R56) ......................................................................................................91
6.41 Main Electronic Volume Register (R57) .......................................................................................................92
6.42 Sub-electronic Volume Register (R58).........................................................................................................92
6.43 RAM Test Mode Setting Register (R61)........................................................................................................93
6.44 Driving Mode Select Register (R64) .............................................................................................................93
6.45 Main R Grayscale Data Registers (R65 to R72) ...........................................................................................94
6.46 Main G Grayscale Data Registers (R73 to R80) ...........................................................................................95
6.47 Main B Grayscale Data Registers (R81 to R84) ...........................................................................................96
6.48 Sub R Grayscale Data Registers (R85 to R92).............................................................................................97
6.49 Sub G Grayscale Data Registers (R93 to R100) ..........................................................................................98
6.50 Sub B Grayscale Data Registers (R101 to R104).........................................................................................99
7.
µ
PD161401 REGISTER LIST ................................................................................................................ 100
8. POWER SEQUENCE............................................................................................................................. 102
8.1 Power ON Sequence (with Internal Power Supply, Power ON
→
Display ON) ........................................103
8.2 Power OFF Sequence (with Internal Power Supply) ...................................................................................105
8.3 Power ON Sequence (with External Driving Power Supply, Power ON
→
Display ON)...........................106
8.4 Power OFF Sequence (with External Driving Power Supply).....................................................................107
8.5 Flow of V
OUT
and V
LCD
Voltages from Power ON to Power OFF .................................................................108
8.6 Flow of V
OUT
and V
LCD
Voltages in Display Output and HALT/Standby Modes.........................................109
9. USING RAM TEST MODE ..................................................................................................................... 110
10. ELECTRICAL SPECIFICATIONS........................................................................................................ 111
11. CPU INTERFACE (Reference Example)............................................................................................ 120
4
Data Sheet S15726EJ2V0DS
µ
PD161401
1. BLOCK DIAGRAM
SEG
1
SEG
303
O
1
O
80
Common driver
Segment driver
Segment gray-scale control
IFM0
IFM1
/CS1
CS2
/RD(E)
/WR(R,/W)
D15 to D8
D7(SI)
D6(SCL)
D5 to D0
RS
/DISP
TOUT15 to TOUT0
M,/S
FR
FRSYNC
DOF
TSTRTST
TSTVIHL
TPWR0, TPWR1
Data
register
Data
control
Address
control
I/O
buffer
Graphic control
Common timing
generator
Display data latch
Display data RAM
101 x 8 x 80 bits
Blink & Inverse data RAM
303 bits
Logic Control Circuit
Command
decorder
OSCIN1
OSCIN2
OSCOUT
OSCSYNC
Oscillator
circuit
Register
Gray-scale
control
V
DD1
V
DD2
Timing generator
V
SS
C1 + C1 -
,
DC/DC
converter
C5 +C5 -
,
D/A
converter
Op amp.
LCD voltage generator
VOUT VOUT2
VRS IRS
VR
AMPOUTM AMPOUTS
VLCD
VLC1
VLC2
VLC3
VLC4
Remark
/xxx is an active-low signal.
Data Sheet S15726EJ2V0DS
5
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