(Note 4) ............................................... –40°C to 85°C
Specified Temperature Range (Note 5)
LTC6405I.............................................. –40°C to 85°C
LTC6405C ................................................ 0°C to 70°C
Junction Temperature ........................................... 150°C
Storage Temperature Range................... –65°C to 150°C
PIN CONFIGURATION
TOP VIEW
–OUTF
12 V
–
17
11 V
+
10 V
+
9
5
V
TIP
6
–IN
7
+OUT
8
+OUTF
V
–
–OUT
+IN
NC
TOP VIEW
–IN 1
V
OCM
2
V
+
3
+OUT 4
9
8
7
6
5
+IN
SHDN
V
–
–OUT
SHDN
V
+
V
–
V
OCM
1
2
3
4
MS8E PACKAGE
8-LEAD PLASTIC MSOP
T
JMAX
= 150°C,
θ
JA
= 40°C/W,
θ
JC
= 10°C/W
EXPOSED PAD (PIN 9) IS V
–
, MUST BE SOLDERED TO PCB
16 15 14 13
UD PACKAGE
16-LEAD (3mm
×
3mm) PLASTIC QFN
T
JMAX
= 150°C,
θ
JA
= 68°C/W,
θ
JC
= 4.2°C/W
EXPOSED PAD (PIN 17) IS V
–
, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
LTC6405CMS8E#PBF
LTC6405IMS8E#PBF
LTC6405CUD#PBF
LTC6405IUD#PBF
TAPE AND REEL
LTC6405CMS8E#TRPBF
LTC6405IMS8E#TRPBF
LTC6405CUD#TRPBF
LTC6405IUD#TRPBF
PART MARKING*
LTDKN
LTDKN
LDKP
LDKP
PACKAGE DESCRIPTION
8-Lead Plastic MSOP
8-Lead Plastic MSOP
16-Lead (3mm
×
3mm) Plastic QFN
16-Lead (3mm
×
3mm) Plastic QFN
SPECIFIED TEMPERATURE RANGE
0°C to 70°C
–40°C to 85°C
0°C to 70°C
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to:
http://www.linear.com/leadfree/
This product is only offered in trays. For more information go to:
http://www.linear.com/packaging/
6405fa
2
LTC6405
DC ELECTRICAL CHARACTERISTICS
SYMBOL
V
OSDIFF
PARAMETER
Differential Offset Voltage (Input Referred)
The
l
denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at T
A
= 25°C. V
+
= 5V, V
–
= 0V, V
CM
= V
OCM
= V
ICM
= 2.5V, V
SHDN
= open,
circuit component values in Figure 1 used, unless otherwise noted. V
S
is defined as (V
+
– V
–
). V
OUTCM
is defined as (V
+OUT
+ V
–OUT
)/2.
V
ICM
is defined as (V
+IN
+ V
–IN
)/2. V
OUTDIFF
is defined as (V
+OUT
– V
–OUT
).
CONDITIONS
V
ICM
= 5V (Note 12)
V
ICM
= 2.5V
V
ICM
= 0V (Note 12)
V
ICM
= 5V (Note 12)
V
ICM
= 2.5V
V
ICM
= 0V (Note 12)
V
ICM
= 5V
V
ICM
= 2.5V
V
ICM
= 0V
V
ICM
= 5V
V
ICM
= 2.5V
V
ICM
= 0V
Common Mode
Differential Mode
Differential
f = 1MHz, Not Including R
I
/R
F
Noise
f = 1MHz, Not Including R
I
/R
F
Noise
f = 1MHz
Op-Amp Inputs
V
ICM
from 0V to 5V
V
OCM
from 0.5V to 3.9V
V
S
= 4.5V to 5.5V
V
S
= 4.5V to 5.5V
V
OCM
from 0.5V to 3.9V
V
OCM
from 0.5V to 3.9V
ΔV
OUTDIFF
= 2V
Single-Ended Input
Differential Input
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
MIN
TYP
±1
±0.5
±1
1.5
1
3
8
–7
–14
±0.5
±0.5
±0.5
230
3.5
1
1.6
2.4
9.5
MAX
±7
±3.5
±7
UNITS
mV
mV
mV
μV/°C
μV/°C
μV/°C
μA
μA
μA
μA
μA
μA
kΩ
kΩ
pF
nV/√Hz
pA/√Hz
nV/√Hz
ΔV
OSDIFF
/ΔT
Differential Offset Voltage Drift (Input Referred)
I
B
Input Bias Current (Note 6)
–24
I
OS
Input Offset Current (Note 6)
l
±4
R
IN
C
IN
e
n
i
n
e
nVOCM
V
ICMR
(Note 7)
CMRRI
(Note 8)
CMRRIO
(Note 8)
PSRR
(Note 9)
PSRRCM
(Note 9)
G
CM
ΔG
CM
BAL
Input Resistance
Input Capacitance
Differential Input Referred Noise Voltage Density
Input Noise Current Density
Input Referred Common Mode Output Noise Voltage
Density
Input Signal Common Mode Range
Input Common Mode Rejection Ratio
(Input Referred) ΔV
ICM
/ΔV
OSDIFF
Output Common Mode Rejection Ratio
(Input Referred) ΔV
OCM
/ΔV
OSDIFF
Differential Power Supply Rejection
(ΔV
S
/ΔV
OSDIFF
)
Output Common Mode Power Supply Rejection
(ΔV
S
/ΔV
OSCM
)
Common Mode Gain (ΔV
OUTCM
/ΔV
OCM
)
Common Mode Gain Error 100 • (G
CM
– 1)
Output Balance (ΔV
OUTCM
/ΔV
OUTDIFF
)
V
–
50
50
50
55
75
75
75
70
1
±0.25
–60
–65
±6
20
0.5
13
2.35
3.9
3.85
19
2.5
4
3.95
0.3
0.42
±60
V
+
V
dB
dB
dB
dB
V/V
±0.8
–40
–40
±15
3.9
25
2.65
%
dB
dB
mV
μV/°C
V
kΩ
V
V
V
V
V
mA
V
OSCM
ΔV
OSCM
/ΔT
V
OUTCMR
(Note 7)
R
INVOCM
V
OCM
V
OUT
Common Mode Offset Voltage (V
OUTCM
– V
OCM
)
Common Mode Offset Voltage Drift
Output Signal Common Mode Range
(Voltage Range for the V
OCM
Pin)
Input Resistance, V
OCM
Pin
Self-Biased Voltage at the V
OCM
Pin
Output Voltage, High, +OUT/–OUT Pins
Output Voltage, Low, +OUT/–OUT Pins
V
OCM
= Open
I
L
= 0
I
L
= –5mA
I
L
= 0
I
L
= 5mA
l
l
l
l
l
l
0.4
0.54
I
SC
Output Short-Circuit Current, +OUT/–OUT Pins
(Note 10)
±40
6405fa
3
LTC6405
DC ELECTRICAL CHARACTERISTICS
SYMBOL
A
VOL
V
S
I
S
I
SHDN
R
SHDN
V
IL
V
IH
t
ON
t
OFF
PARAMETER
Large-Signal Open Loop Voltage Gain
Supply Voltage Range
Supply Current
Supply Current in Shutdown
SHDN
Pull-Up Resistor
SHDN
Input Logic Low
SHDN
Input Logic High
Turn-On Time
Turn-Off Time
V
SHDN
= 0V
V
SHDN
= 0V to 0.5V
l
l
l
l
l
l
The
l
denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at T
A
= 25°C. V
+
= 5V, V
–
= 0V, V
CM
= V
OCM
= V
ICM
= 2.5V, V
SHDN
= open,
circuit component values in Figure 1 used, unless otherwise noted. V
S
is defined as (V
+
– V
–
). V
OUTCM
is defined as (V
+OUT
+ V
–OUT
)/2.
V
ICM
is defined as (V
+IN
+ V
–IN
)/2. V
OUTDIFF
is defined as (V
+OUT
– V
–OUT
).
CONDITIONS
MIN
4.5
18
0.4
30
1.25
50
1.8
2
200
50
2.55
TYP
90
5.5
23
1
70
MAX
UNITS
dB
V
mA
mA
kΩ
V
V
ns
ns
AC ELECTRICAL CHARACTERISTICS
SYMBOL
SR
GBW
f
–3dB
PARAMETER
Slew Rate
Gain-Bandwidth Product
–3dB Frequency (See Figure 2)
50MHz Distortion
Differential Input, V
OUTDIFF
= 2V
P-P
(Note 13)
The
l
denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at T
A
= 25°C. V
+
= 5V, V
–
= 0V, V
CM
= V
OCM
= V
ICM
= 2.5V, V
SHDN
= open,
R
LOAD
= 400Ω, circuit component values in Figure 2 used, unless otherwise noted. V
S
is defined as (V
+
– V
–
). V
ICM
is defined as (V
+IN
+ V
–IN
)/2. V
OUTDIFF
is defined as (V
+OUT
– V
–OUT
).
CONDITIONS
Differential Output
f
TEST
= 27MHz
QFN Package
MSOP Package
V
OCM
= 2.5V, V
S
= 5V
2nd Harmonic
3rd Harmonic
V
OCM
= 2.5V, V
S
= 5V, R
LOAD
= 800Ω
2nd Harmonic
3rd Harmonic
V
OCM
= 2.5V, V
S
= 5V, R
LOAD
= 800Ω,
R
I
= R
F
= 499Ω
2nd Harmonic
3rd Harmonic
50MHz Distortion
Single-Ended Input, V
OUTDIFF
= 2V
P-P
(Note 13)
3rd-Order IMD at 49.5MHz, 50.5MHz
Equivalent OIP3 at 50MHz (Note 11)
V
OCM
= 2.5V, V
S
= 5V, R
LOAD
= 800Ω,
R
I
= R
F
= 499Ω
2nd Harmonic
3rd Harmonic
V
OUTDIFF
= 2V
P-P
Envelope,
R
LOAD
= 800Ω
R
LOAD
= 800Ω
V
OUTDIFF
= 2V Step
1% Settling
0.1% Settling
Shunt-Terminated to 50Ω, R
S
= 50Ω
Z
IN
= 200Ω (R
I
= 100Ω, R
F
= 300Ω)
500
400
MIN
TYP
690
2.7
800
750
–80
–64
–82
–66
MAX
UNITS
V/μS
GHz
MHz
MHz
dBc
dBc
dBc
dBc
l
–53
–82
–64
dBc
dBc
–72
–77
–63
35.5
6
11
14.4
7.5
dBc
dBc
dBc
dBm
ns
ns
dB
dB
t
S
Settling Time
NF
Noise Figure at 50MHz
6405fa
4
LTC6405
ELECTRICAL CHARACTERISTICS
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2:
Input pins (+IN, –IN, V
OCM
,
SHDN
and V
TIP
) are protected by
steering diodes to either supply. If the inputs should exceed either supply
voltage, the input current should be limited to less than 10mA. In addition,
the inputs +IN, –IN are protected by a pair of back-to-back diodes. If the
differential input voltage exceeds 1.4V, the input current should be limited
to less than 10mA.
Note 3:
A heat sink may be required to keep the junction temperature
below the Absolute Maximum Rating when the output is shorted
indefinitely.
Note 4:
The LTC6405C/LTC6405I are guaranteed functional over the
operating temperature range –40°C to 85°C.
Note 5:
The LTC6405C is guaranteed to meet specified performance from
0°C to 70°C. The LTC6405C is designed, characterized, and expected
to meet specified performance from –40°C to 85°C but is not tested or
QA sampled at these temperatures. The LTC6405I is guaranteed to meet
specified performance from –40°C to 85°C.
Note 6:
Input bias current is defined as the average of the input currents
flowing into the inputs (–IN, and +IN). Input Offset current is defined as
the difference between the input currents (I
OS
= I
B+
– I
B–
).
Note 7:
Input common mode range is tested using the test circuit of Figure
1 by taking 3 measurements of differential gain with a ±1VDC differential
output with V
ICM
= 0V; V
ICM
= 2.5V; V
ICM
= 5V, verifying that the differential
gain has not deviated from the V
ICM
= 2.5V case by more than 0.5%, and
that the common mode offset (V
OSCM
) has not deviated from the common
mode offset at V
ICM
= 2.5V by more than ±35mV.
The voltage range for the output common mode range is tested using the
test circuit of Figure 1 by applying a voltage on the V
OCM
pin and testing at
both V
OCM
= 2.5V and at the Electrical Characteristics table limits to verify
that the common mode offset (V
OSCM
) has not deviated by more than
±20mV from the V
OCM
= 2.5V case.
Note 8:
Input CMRR is defined as the ratio of the change in the input
common mode voltage at the pins +IN or –IN to the change in differential
input referred voltage offset. Output CMRR is defined as the ratio of
the change in the voltage at the V
OCM
pin to the change in differential
input referred voltage offset. This specification is strongly dependent on
feedback ratio matching between the two outputs and their respective
inputs, and it is difficult to measure actual amplifier performance. (See
the “Effects of Resistor Pair Mismatch” in the Applications Information
section of this data sheet.) For a better indicator of actual amplifier
performance independent of feedback component matching, refer to the
PSRR specification.
Note 9:
Differential Power Supply Rejection (PSRR) is defined as the
ratio of the change in supply voltage to the change in differential input
referred voltage offset. Common mode power supply rejection (PSRRCM)
is defined as the ratio of the change in supply voltage to the change in the
common mode offset, V
OUTCM
– V
OCM
.
Note 10:
Extended operation with the output shorted may cause the
junction temperature to exceed the 150°C limit.
Note 11:
Because the LTC6405 is a feedback amplifier with low output
impedance, a resistive load is not required when driving an ADC.
Therefore, typical output power can be very small in many applications. In
order to compare the LTC6405 with “RF style” amplifiers that require 50Ω
load, the output voltage swing is converted to dBm as if the outputs were
driving a 50Ω load. For example, 2V
P-P
output swing is equal to 10dBm
using this convention.
Note 12:
Includes offset/drift induced by feedback resistors mismatch. See
the Applications Information section for more details.
Note 13:
QFN package only—refer to datasheet curves for MSOP package
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
