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Intel 810E Chipset: 82810E
Graphics and Memory Controller
Hub (GMCH)
Datasheet
September 1999
®
Order Number:
290676-001
Intel 82810E (GMCH)
®
R
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended
for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future
definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel
®
810E may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current
characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
I
2
C is a 2-wire communications bus/protocol developed by Philips. SMBus is a subset of the I
2
C bus/protocol and was developed by Intel.
Implementations of the I
2
C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips
Corporation.
Alert on LAN is a result of the Intel-IBM Advanced Manageability Alliance and a trademark of IBM
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from:
Intel Corporation
or call 1-800-548-4725
*Third-party brands and names are the property of their respective owners.
Copyright © Intel Corporation 1998, 1999
2
Datasheet
R
Intel 82810E (GMCH)
®
Contents
1.
Overview .................................................................................................................................... 11
1.1.
1.2.
1.3.
1.4.
1.5.
1.6.
1.7.
1.8.
1.9.
2.
The Intel 810E Chipset System.................................................................................... 11
GMCH Overview............................................................................................................ 13
Host Interface ................................................................................................................ 14
System Memory Interface ............................................................................................. 14
Display Cache Interface ................................................................................................ 14
Hub Interface................................................................................................................. 15
GMCH Graphics Support .............................................................................................. 15
1.7.1. Display, Digital Video Out, and LCD/Flat Panel................................................ 15
System Clocking............................................................................................................ 16
References .................................................................................................................... 16
®
Signal Description ...................................................................................................................... 17
2.1.
2.2.
2.3.
2.4.
2.5.
2.6.
2.7.
2.8.
2.9.
2.10.
Host Interface Signals ................................................................................................... 18
System Memory Interface Signals................................................................................. 19
Display Cache Interface Signals.................................................................................... 20
Hub Interface Signals .................................................................................................... 20
Display Interface Signals ............................................................................................... 21
Digital Video Output Signals/TV-Out Pins ..................................................................... 22
Power Signals................................................................................................................ 23
Clock Signals................................................................................................................. 23
Miscellaneous Interface Signals .................................................................................... 24
Power-Up/Reset Strap Options ..................................................................................... 24
3.
Configuration Registers.............................................................................................................. 25
3.1.
3.2.
Register Nomenclature and Access Attributes.............................................................. 25
PCI Configuration Space Access .................................................................................. 26
3.2.1. PCI Bus Configuration Mechanism................................................................... 26
3.2.2. Logical PCI Bus #0 Configuration Mechanism ................................................. 27
3.2.3. Primary PCI (PCI0) and Downstream Configuration Mechanism..................... 27
3.2.4. Internal Graphics Device Configuration Mechanism ........................................ 27
3.2.5. GMCH Register Introduction............................................................................. 27
I/O Mapped Registers ................................................................................................... 28
3.3.1. CONFIG_ADDRESSConfiguration Address Register................................... 28
3.3.2. CONFIG_DATAConfiguration Data Register ................................................ 29
Host-Hub Interface Bridge/DRAM Controller Device Registers (Device 0) ................... 30
3.4.1. VIDVendor Identification Register (Device 0)................................................ 31
3.4.2. DIDDevice Identification Register (Device 0) ................................................ 31
3.4.3. PCICMDPCI Command Register (Device 0) ................................................ 32
3.4.4. PCISTSPCI Status Register (Device 0) ........................................................ 33
3.4.5. RIDRevision Identification Register (Device 0) ............................................. 34
3.4.6. SUBCSub-Class Code Register (Device 0) .................................................. 34
3.4.7. BCCBase Class Code Register (Device 0) ................................................... 34
3.4.8. MLTMaster Latency Timer Register (Device 0) ............................................ 35
3.4.9. HDRHeader Type Register (Device 0).......................................................... 35
3.4.10. SVIDSubsystem Vendor Identification Register (Device 0) .......................... 35
3
3.3.
3.4.
Datasheet
Intel 82810E (GMCH)
3.4.11. SIDSubsystem Identification Register (Device 0) ..........................................36
3.4.12. CAPPTRCapabilities Pointer (Device 0)........................................................36
3.4.13. GMCHCFGGMCH Configuration Register (Device 0)...................................37
3.4.14. PAMR—Programmable Attributes Register (Device 0).....................................38
3.4.15. DRPDRAM Row Population Register (Device 0)...........................................39
3.4.16. DRAMTDRAM Timing Register (Device 0)....................................................41
3.4.17. FCHCFixed DRAM Hole Control Register (Device 0) ...................................42
3.4.18. SMRAMSystem Management RAM Control Register (Device 0).................43
3.4.19. MISCCMiscellaneous Control Register (Device 0) ........................................45
3.4.20. MISCC2Miscellaneous Control 2 Register (Device 0) ...................................46
3.4.21. BUFF_SC—System Memory Buffer Strength Control Register (Device 0).......47
Graphics Device Registers (Device 1) ...........................................................................49
3.5.1. VIDVendor Identification Register (Device 1) ................................................50
3.5.2. DIDDevice Identification Register (Device 1) ................................................50
3.5.3. PCICMDPCI Command Register (Device 1) .................................................51
3.5.4. PCISTSPCI Status Register (Device 1).........................................................52
3.5.5. RIDRevision Identification Register (Device 1)..............................................53
3.5.6. PI-Programming Interface Register (Device 1) .................................................53
3.5.7. SUBC1—Sub-Class Code Register (Device 1).................................................53
3.5.8. BCC1—Base Class Code Register (Device 1) .................................................54
3.5.9. CLSCache Line Size Register (Device 1)......................................................54
3.5.10. MLTMaster Latency Timer Register (Device 1).............................................54
3.5.11. HDRHeader Type Register (Device 1) ..........................................................55
3.5.12. BISTBuilt In Self Test (BIST) Register (Device 1) .........................................55
3.5.13. GMADRGraphics Memory Range Address Register (Device 1) ...................56
3.5.14. MMADRMemory Mapped Range Address Register (Device 1) ....................57
3.5.15. SVIDSubsystem Vendor Identification Register (Device 1) ...........................57
3.5.16. SIDSubsystem Identification Register (Device 1) ..........................................58
3.5.17. ROMADRVideo BIOS ROM Base Address Registers (Device 1) ................58
3.5.18. CAPPOINTCapabilities Pointer Register (Device 1) .....................................58
3.5.19. INTRLINEInterrupt Line Register (Device 1) .................................................59
3.5.20. INTRPINInterrupt Pin Register (Device 1).....................................................59
3.5.21. MINGNTMinimum Grant Register (Device 1)................................................59
3.5.22. MAXLATMaximum Latency Register (Device 1) ...........................................59
3.5.23. PM_CAPIDPower Management Capabilities ID Register (Device 1) ............60
3.5.24. PM_CAPPower Management Capabilities Register (Device 1) ....................60
3.5.25. PM_CS—Power Management Control/Status Register (Device 1) .................62
Display Cache Interface.................................................................................................63
3.6.1. DRT—DRAM Row Type....................................................................................63
3.6.2. DRAMCL—DRAM Control Low.........................................................................64
3.6.3. DRAMCH—DRAM Control High .......................................................................65
Display Cache Detect and Diagnostic Registers ...........................................................66
3.7.1. GRXGRX Graphics Controller Index Register...............................................66
3.7.2. MSRMiscellaneous Output ............................................................................67
3.7.3. GR06Miscellaneous Register ........................................................................68
3.7.4. GR10Address Mapping .................................................................................69
3.7.5. GR11Page Selector.......................................................................................69
®
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3.5.
3.6.
3.7.
4
Datasheet
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