TECHNICAL INFORMATION
Stereo 10W (4Ω) Class-T™ Digital Audio Amplifier using
Ω
Digital Power Processing™ Technology
TA1101B
September 2000
General Description
The TA1101B is a 10W continuous average two-channel Class-T Digital Audio Power
Amplifier IC using Tripath’s proprietary Digital Power Processing™ technology. Class-T
amplifiers offer both the audio fidelity of Class-AB and the power efficiency of Class-D
amplifiers.
Applications
!"Computer/PC
Multimedia
!"DVD
Players
!"Cable
Set-Top Products
!"Televisions
!"Video
CD Players
!"Battery
Powered Systems
Features
!"Class-T
architecture
!"Single
Supply Operation
!"“Audiophile”
Quality Sound
!"0.04%
THD+N @ 9W, 4Ω
!"0.18%
IHF-IM @ 1W, 4Ω
!"6W
@ 8Ω, 0.1% THD+N
!"11W
@ 4Ω, 0.1% THD+N
!"High
Power
!"10W
@ 8Ω, 10% THD+N
!"15W
@ 4Ω, 10% THD+N
!"High
Efficiency
!"88%
@ 10W, 8Ω
!"81%
@ 15W, 4Ω
!"Dynamic
Range = 102 dB
!"Mute
and Sleep inputs
!"Turn-on
& turn-off pop suppression
!"Over-current
protection
!"Over-temperature
protection
!"Bridged
outputs
!"30-pin
Power SOP package
Benefits
!"Fully
integrated solution with FETs
!"Easier
to design-in than Class-D
!"Reduced
system cost with no heat sink
!"Dramatically
improves efficiency versus
Class-AB
!"Signal
fidelity equal to high quality linear
amplifiers
!"High
dynamic range compatible with digital
media such as CD, DVD, and Internet audio
Typical Performance
THD+N versus Output Power
10
5
VDD = 12V
f = 1kHz
Av = 12
BW = 22Hz - 22kHz
2
1
THD+N (%)
0.5
0.2
0.1
0.05
R
L
= 8Ω
R
L
= 4Ω
0.02
0.01
500m
1
2
5
10
20
Output Power (W)
TA1101B, Rev. 2.2, 08.17.00
1
TECHNICAL INFORMATION
Absolute Maximum Ratings
(Note 1)
SYMBOL
V
DD
T
STORE
T
A
P
DISS
Supply Voltage
Storage Temperature Range
Operating Free-air Temperature Range
Continuous Total Power Dissipation
PARAMETER
Value
16
-40
°
to 150
°
0
°
to 70
°
Note 2
UNITS
V
C
C
W
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
Note 2: See Power Dissipation Derating in the Applications Information section.
Operating Conditions
(Note 3)
SYMBOL
V
DD
V
IH
V
IL
Supply Voltage
High-level Input Voltage (MUTE, SLEEP)
Low-level Input Voltage (MUTE, SLEEP)
PARAMETER
MIN.
8.5
3.5
1
TYP.
12
MAX.
13.2
UNITS
V
V
V
Note 3: Recommended Operating Conditions indicate conditions for which the device is functional. See
Electrical Characteristics for guaranteed specific performance limits.
Electrical Characteristics
See Test/Application Circuit. Unless otherwise specified, V
DD
= 12V, f = 1kHz, Measurement
Bandwidth = 22kHz, R
L
= 4Ω, T
A
= 25
°C,
Package heat slug soldered to 2.8 square-inch PC pad.
SYMBOL
P
O
PARAMETER
Output Power
(Continuous Average/Channel)
CONDITIONS
THD+N = 0.1%
THD+N = 10%
I
DD,MUTE
I
DD, SLEEP
I
q
THD + N
IHF-IM
SNR
CS
PSRR
η
V
OFFSET
V
OH
V
OL
e
OUT
Mute Supply Current
Sleep Supply Current
Quiescent Current
Total Harmonic Distortion Plus
Noise
IHF Intermodulation Distortion
Signal-to-Noise Ratio
Channel Separation
Power Supply Rejection Ratio
Power Efficiency
Output Offset Voltage
High-level output voltage
(FAULT & OVERLOAD)
Low-level output voltage
(FAULT & OVERLOAD)
Output Noise Voltage
MUTE = V
IH
SLEEP = V
IH
V
IN
= 0 V
P
O
= 9W/Channel
19kHz, 20kHz, 1:1 (IHF)
A-Weighted, P
OUT
= 1W, R
L
= 8Ω
30kHz Bandwidth
Vripple = 100mV.
P
OUT
= 10W/Channel, R
L
= 8Ω
No Load, MUTE = Logic Low
3.5
1
A-Weighted, input AC grounded
100
50
60
R
L
= 4Ω
R
L
= 8Ω
R
L
= 4Ω
R
L
= 8Ω
MIN.
9
5.5
12
8
TYP.
11
6
16
10
5.5
0.25
61
0.04
0.18
89
55
80
88
50
150
0.5
7
2
75
MAX.
UNITS
W
W
W
W
mA
mA
mA
%
%
dB
dB
dB
%
mV
V
V
µV
Note:
Minimum and maximum limits are guaranteed but may not be 100% tested.
2
TA1101B, Rev. 2.2, 08.17.00
TECHNICAL INFORMATION
Pin Description
Pin
1, 2
Function
DCAP2, DCAP1
Description
Charge pump switching pins. DCAP1 (pin 2) is a free running 300kHz square
wave between VDDA and DGND (12Vpp nominal). DCAP2 (pin 1) is level shifted
10 volts above DCAP1 (pin 2) with the same amplitude (12Vpp nominal),
frequency, and phase as DCAP1.
Digital 5VDC, Analog 5VDC
Analog Ground
Internal reference voltage; approximately 1.0 VDC.
A logic low output indicates the input signal has overloaded the amplifier.
Input stage output pins.
Single-ended inputs. Inputs are a “virtual” ground of an inverting opamp with
approximately 2.4VDC bias.
When set to logic high, both amplifiers are muted and in idle mode. When low
(grounded), both amplifiers are fully operational. If left floating, the device stays in
the mute mode. Ground if not used.
Input stage bias voltage (approximately 2.4VDC).
When set to logic high, device goes into low power mode. If not used, this pin
should be grounded
A logic high output indicates thermal overload, or an output is shorted to ground,
or another output.
Power Grounds (high current)
Digital Ground
Bridged outputs
Supply pins for high current H-bridges, nominally 12VDC.
Not connected
Analog 12VDC
Charge pump output (nominally 10V above VDDA)
Regulated 5VDC source used to supply power to the input section (pins 3 and 8).
3, 8
4, 7,
15
5
6
9, 12
10, 13
11
V5D, V5A
AGND1, AGND2,
AGND3
REF
OVERLOADB
VP1, VP2
IN1, IN2
MUTE
14
16
17
18, 28
19
20, 22;
25, 23
21, 24
26
27
29
30
BIASCAP
SLEEP
FAULT
PGND2, PGND1
DGND
OUTP2 & OUTM2;
OUTP1 & OUTM1
VDD2, VDD1
NC
VDDA
CPUMP
5VGEN
30-pin Power SOP Package
(Top View)
DCAP2
DCAP1
V5D
AGND1
REF
OVERLOADB
AGND2
V5A
VP1
IN1
MUTE
VP2
IN2
BIASCAP
AGND3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
5VGEN
CPUMP
PGND1
VDDA
NC
OUTP1
VDD1
OUTM1
OUTM2
VDD2
OUTP2
DGND
PGND2
FAULT
SLEEP
TA1101B, Rev. 2.2, 08.17.00
3
TECHNICAL INFORMATION
Application / Test Circuit
4
TA1101B, Rev. 2.2, 08.17.00
TECHNICAL INFORMATION
TA1101B
VDD1
L
o
10uH, 2A
C
I
2.2uF
+
R
F
20KΩ
VP1
9
25
OUTP1
D
O
IN1
R
I
20KΩ
C
A
0.1uF
10
Processing
&
Modulation
PGND1
VDD1
(Pin 28)
(Pin 28)
*C
o
0.47uF
C
Z
0.47uF
C
CM
0.1uF
R
Z
10Ω, 1/2W
R
L
4Ω or *8Ω
BIASCAP
5V
MUTE
14
5V
23
OUTM1
D
O
(Pin 28)
L
o
10uH, 2A
*C
o
0.47uF
(Pin 7)
11
PGND1
17
6
VP2
12
C
I
2.2uF
+
R
F
20KΩ
IN2
R
I
20KΩ
VDD2
FAULT
OVERLOADB
13
20
OUTP2
D
O
L
o
10uH, 2A
5
(Pin 7)
R
REF
8.25KΩ, 1%
REF
Processing
&
Modulation
PGND2
VDD2
(Pin 18)
(Pin 18)
*C
o
0.47uF
C
Z
0.47uF
C
CM
0.1uF
+12V
C
D
0.1uF
2
DCAP1
22
OUTM2
D
O
L
o
10uH, 2A
R
Z
*C
o
0.47uF 10Ω, 1/2W
R
L
4Ω or *8Ω
1
1megΩ
DCAP2
PGND2
SLEEP
CPUMP
29
(Pin 18)
16
0.1uF
26
NC
3
+
5V
27
VDDA
DGND
C
P
1uF
C
S
0.1uF
C
S
0.1uF
V5D
AGND1
V5A
19
C
S
0.1uF
To Pin 30
C
S
0.1uF
4
8
5VGEN
30
VDD1
To Pin 3,8
VDD (+12V)
C
SW
24
C
SW
0.1uF
+
7
AGND2
15
AGND3
PGND1
28
180uF, 16V
VDD2
PGND2
21
18
C
SW
0.1uF
+
C
SW
180uF, 16V
Note: Analog and Digital/Power Grounds must
be connected locally at the TA1101B
Analog Ground
Digital/Power Ground
All Diodes Motorola MBRS130T3
* Use C
o
= 0.22µF for 8 Ohm loads
TA1101B, Rev. 2.2, 08.17.00
5
DSP 与 ARM 处理器
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
