FM22LD16
4-Mbit (256K × 16) F-RAM Memory
4-Mbit (256K × 16) F-RAM Memory
Features
■
Functional Overview
The FM22LD16 is a 256K × 16 nonvolatile memory that reads
and writes similar to a standard SRAM. A ferroelectric random
access memory or F-RAM is nonvolatile, which means that data
is retained after power is removed. It provides data retention for
over 151 years while eliminating the reliability concerns,
functional disadvantages, and system design complexities of
battery-backed SRAM (BBSRAM). Fast write timing and high
write endurance make the F-RAM superior to other types of
memory.
The FM22LD16 operation is similar to that of other RAM devices
and therefore, it can be used as a drop-in replacement for a
standard SRAM in a system. Read and write cycles may be
triggered by CE or simply by changing the address. The F-RAM
memory is nonvolatile due to its unique ferroelectric memory
process. These features make the FM22LD16 ideal for
nonvolatile memory applications requiring frequent or rapid
writes.
The FM22LD16 includes a low voltage monitor that blocks
access to the memory array when V
DD
drops below V
DD
min.
The memory is protected against an inadvertent access and data
corruption under this condition. The device also features
software-controlled write protection. The memory array is
divided into 8 uniform blocks, each of which can be individually
write protected.
The device is available in a 48-ball FBGA package. Device
specifications are guaranteed over the industrial temperature
range –40 °C to +85 °C.
For a complete list of related documentation, click
here.
4-Mbit ferroelectric random access memory (F-RAM) logically
organized as 256K × 16
❐
Configurable as 512K × 8 using UB and LB
14
❐
High-endurance 100 trillion (10 ) read/writes
❐
151-year data retention (see the
Data Retention and
Endurance
table)
❐
NoDelay™ writes
❐
Page mode operation to 25-ns cycle time
❐
Advanced high-reliability ferroelectric process
SRAM compatible
❐
Industry-standard 256K × 16 SRAM pinout
❐
55-ns access time, 110-ns cycle time
Advanced features
❐
Software-programmable block write-protect
Superior to battery-backed SRAM modules
❐
No battery concerns
❐
Monolithic reliability
❐
True surface mount solution, no rework steps
❐
Superior for moisture, shock, and vibration
Low power consumption
❐
Active current 8 mA (typ)
❐
Standby current 90
A
(typ)
Low-voltage operation: V
DD
= 2.7 V to 3.6 V
Industrial temperature: –40
C
to +85
C
48-ball fine-pitch ball grid array (FBGA) package
Restriction of hazardous substances (RoHS) compliant
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Logic Block Diagram
32 K x 16 block
Address Latch & Write Protect
32 K x 16 block
Block & Row Decoder
32 K x 16 block
32 K x 16 block
A17-0
...
32 K x 16 block
A 17-2
32 K x 16 block
A 1-0
32 K x 16 block
32 K x 16 block
CE
WE
UB, LB
OE
Control
Logic
...
Column Decoder
I/O Latch & Bus Driver
DQ15-0
Cypress Semiconductor Corporation
Document Number: 001-86190 Rev. *F
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised November 9, 2017
FM22LD16
Contents
Pinout ................................................................................ 3
Pin Definitions .................................................................. 3
Device Operation .............................................................. 4
Memory Operation ....................................................... 4
Read Operation ........................................................... 4
Write Operation ........................................................... 4
Page Mode Operation ................................................. 4
Pre-charge Operation .................................................. 4
Software Write Protect ................................................ 4
Software Write-Protect Timing .................................... 7
SRAM Drop-In Replacement ....................................... 8
Maximum Ratings ............................................................. 9
Operating Range ............................................................... 9
DC Electrical Characteristics .......................................... 9
Data Retention and Endurance ....................................... 9
Capacitance .................................................................... 10
Thermal Resistance ........................................................ 10
AC Test Conditions ........................................................ 10
AC Switching Characteristics ....................................... 11
SRAM Read Cycle .................................................... 11
SRAM Write Cycle ..................................................... 12
Power Cycle and Sleep Mode Timing ........................... 16
Functional Truth Table ................................................... 17
Ordering Information ...................................................... 18
Ordering Code Definitions ......................................... 18
Package Diagram ............................................................ 19
Acronyms ........................................................................ 20
Document Conventions ................................................. 20
Units of Measure ....................................................... 20
Document History Page ................................................. 21
Sales, Solutions, and Legal Information ...................... 22
Worldwide Sales and Design Support ....................... 22
Products .................................................................... 22
PSoC® Solutions ...................................................... 22
Cypress Developer Community ................................. 22
Technical Support ..................................................... 22
Document Number: 001-86190 Rev. *F
Page 2 of 22
FM22LD16
Pinout
Figure 1. 48-ball FBGA pinout
(× 16)
Top View
(not to scale)
1
LB
DQ
8
2
OE
UB
3
A
0
A
3
A
5
A
17
NC
A
14
A
12
A
9
4
A
1
A
4
A
6
A
7
A
16
A
15
A
13
A
10
5
A
2
CE
DQ
1
DQ
3
DQ
4
DQ
5
WE
A
11
6
NC
DQ
0
DQ
2
V
DD
V
SS
DQ
6
DQ
7
NC
A
B
C
D
E
F
G
H
DQ
9
DQ
10
V
SS
DQ
11
V
DD
DQ
12
DQ
14
DQ
13
DQ
15
NC
NC
A
8
Pin Definitions
Pin Name
A
17
–A
0
I/O Type
Input
Description
Address inputs:
The 18 address lines select one of 262,144 words in the F-RAM array. The lowest two
address lines A
1
–A
0
may be used for page mode read and write operations.
Write Enable:
A write cycle begins when WE is asserted. The rising edge causes the FM22LD16 to
write the data on the DQ bus to the F-RAM array. The falling edge of WE latches a new column address
for page mode write cycles.
Chip Enable:
The device is selected and a new memory access begins on the falling edge of CE. The
entire address is latched internally at this point. Subsequent changes to the A
1
–A
0
address inputs allow
page mode operation.
Output Enable:
When OE is LOW, the FM22LD16 drives the data bus when the valid read data is
available. Deasserting OE HIGH tristates the DQ pins.
Upper Byte Select:
Enables DQ
15
–DQ
8
pins during reads and writes. These pins are HI-Z if UB is HIGH.
If the user does not perform byte writes and the device is not configured as a 512K × 8, the UB and LB
pins may be tied to ground.
Lower Byte Select:
Enables DQ
7
–DQ
0
pins during reads and writes. These pins are HI-Z if LB is HIGH.
If the user does not perform byte writes and the device is not configured as a 512K × 8, the UB and LB
pins may be tied to ground.
Ground for the device. Must be connected to the ground of the system.
No connect. This pin is not connected to the die.
DQ
15
–DQ
0
Input/Output
Data I/O Lines:
16-bit bidirectional data bus for accessing the F-RAM array.
WE
Input
CE
Input
OE
UB
Input
Input
LB
Input
V
SS
V
DD
NC
Ground
No connect
Power supply Power supply input to the device.
Document Number: 001-86190 Rev. *F
Page 3 of 22
FM22LD16
Device Operation
The FM22LD16 is a word wide F-RAM memory logically
organized as 262,144 × 16 and accessed using an
industry-standard parallel interface. All data written to the part is
immediately nonvolatile with no delay. The device offers page
mode operation, which provides high-speed access to
addresses within a page (row). Access to a different page
requires that either CE transitions LOW or the upper address
(A
17
–A
2
) changes. See the
Functional Truth Table on page 17
for a complete description of read and write modes.
deasserted HIGH. In a WE-controlled write, the memory cycle
begins on the falling edge of CE. The WE signal falls some time
later. Therefore, the memory cycle begins as a read. The data
bus will be driven if OE is LOW; however, it will be HI-Z when WE
is asserted LOW. The CE- and WE-controlled write timing cases
are shown in the
Figure 11 on page 14.
Write access to the array begins on the falling edge of WE after
the memory cycle is initiated. The write access terminates on the
rising edge of WE or CE, whichever comes first. A valid write
operation requires the user to meet the access time specification
before deasserting WE or CE. The data setup time indicates the
interval during which data cannot change before the end of the
write access (rising edge of WE or CE).
Unlike other nonvolatile memory technologies, there is no write
delay with F-RAM. Because the read and write access times of
the underlying memory are the same, the user experiences no
delay through the bus. The entire memory operation occurs in a
single bus cycle. Data polling, a technique used with EEPROMs
to determine if a write is complete, is unnecessary.
Memory Operation
Users access 262,144 memory locations, each with 16 data bits
through a parallel interface. The F-RAM array is organized as
eight blocks, each having 8192 rows. Each row has four column
locations, which allow fast access in page mode operation.
When an initial address is latched by the falling edge of CE,
subsequent column locations may be accessed without the need
to toggle CE. When CE is deasserted HIGH, a pre-charge
operation begins. Writes occur immediately at the end of the
access with no delay. The WE pin must be toggled for each write
operation. The write data is stored in the nonvolatile memory
array immediately, which is a feature unique to F-RAM called
NoDelay writes.
Page Mode Operation
The F-RAM array is organized as eight blocks, each having 8192
rows. Each row has four column-address locations. Address
inputs A
1
–A
0
define the column address to be accessed. An
access can start on any column address, and other column
locations may be accessed without the need to toggle the CE pin.
For fast access reads, after the first data byte is driven to the bus,
the column address inputs A
1
–A
0
may be changed to a new
value. A new data byte is then driven to the DQ pins no later than
t
AAP
, which is less than half the initial read access time. For fast
access writes, the first write pulse defines the first write access.
While CE is LOW, a subsequent write pulse along with a new
column address provides a page mode write access.
Read Operation
A read operation begins on the falling edge of CE. The falling
edge of CE causes the address to be latched and starts a
memory read cycle if WE is HIGH. Data becomes available on
the bus after the access time is met. When the address is latched
and the access completed, a new access to a random location
(different row) may begin while CE is still LOW. The minimum
cycle time for random addresses is t
RC
. Note that unlike SRAMs,
the FM22LD16's CE-initiated access time is faster than the
address access time.
The FM22LD16 will drive the data bus when OE and at least one
of the byte enables (UB, LB) is asserted LOW. The upper data
byte is driven when UB is LOW, and the lower data byte is driven
when LB is LOW. If OE is asserted after the memory access time
is met, the data bus will be driven with valid data. If OE is
asserted before completing the memory access, the data bus will
not be driven until valid data is available. This feature minimizes
supply current in the system by eliminating transients caused by
invalid data being driven to the bus. When OE is deasserted
HIGH, the data bus will remain in a HI-Z state.
Pre-charge Operation
The pre-charge operation is an internal condition in which the
memory state is prepared for a new access. Pre-charge is
user-initiated by driving the CE signal HIGH. It must remain
HIGH for at least the minimum pre-charge time, t
PC
.
Pre-charge is also activated by changing the upper addresses,
A
17
–A
2
. The current row is first closed before accessing the new
row. The device automatically detects an upper order address
change, which starts a pre-charge operation. The new address
is latched and the new read data is valid within the t
AA
address
access time; see
Figure 8 on page 13.
A similar sequence occurs
for write cycles; see
Figure 13 on page 14.
The rate at which
random addresses can be issued is t
RC
and t
WC
, respectively.
Write Operation
In the FM22LD16, writes occur in the same interval as reads. The
FM22LD16 supports both CE and WE controlled write cycles. In
both cases, the address A
17
–A
2
is latched on the falling edge of
CE.
In a CE-controlled write, the WE signal is asserted before
beginning the memory cycle. That is, WE is LOW when CE falls.
In this case, the device begins the memory cycle as a write. The
FM22LD16 will not drive the data bus regardless of the state of
OE as long as WE is LOW. Input data must be valid when CE is
Software Write Protect
The 256K × 16 address space is divided into eight sectors
(blocks) of 32K × 16 each. Each sector can be individually
software write-protected and the settings are nonvolatile. A
unique address and command sequence invokes the
write-protect mode.
To modify write protection, the system host must issue six read
commands, three write commands, and a final read command.
Document Number: 001-86190 Rev. *F
Page 4 of 22
FM22LD16
The specific sequence of read addresses must be provided to
access the write-protect mode. Following the read address
sequence, the host must write a data byte that specifies the
desired protection state of each sector. For confirmation, the
system must then write the complement of the protection byte
immediately after the protection byte. Any error that occurs
including read addresses in the wrong order, issuing a seventh
read address, or failing to complement the protection value will
leave the write protection unchanged.
The write-protect state machine monitors all addresses, taking
no action until this particular read/write sequence occurs. During
the address sequence, each read will occur as a valid operation
and data from the corresponding addresses will be driven to the
data bus. Any address that occurs out of sequence will cause the
software protection state machine to start over. After the address
sequence is completed, the next operation must be a write cycle.
The lower data byte contains the write-protect settings. This
value will not be written to the memory array, so the address is a
don't-care. Rather it will be held pending the next cycle, which
must be a write of the data complement to the protection settings.
If the complement is correct, the write-protect settings will be
adjusted. Otherwise, the process is aborted and the address
sequence starts over. The data value written after the correct six
addresses will not be entered into the memory.
The protection data byte consists of eight bits, each associated
with the write-protect state of a sector. The data byte must be
driven to the lower eight bits of the data bus, DQ
7
–DQ
0
. Setting
a bit to ‘1’ write-protects the corresponding sector; a ‘0’ enables
writes for that sector. The following table shows the write-protect
sectors with the corresponding bit that controls the write-protect
setting.
Table 1. Write Protect Sectors - 32K x 16 Blocks
Sectors
Sector 7
Sector 6
Sector 5
Sector 4
Sector 3
Sector 2
Sector 1
Sector 0
Blocks
3FFFFh–38000h
37FFFh–30000h
2FFFFh–28000h
27FFFh–20000h
1FFFFh–18000h
17FFFh–10000h
0FFFFh–08000h
07FFFh–00000h
The write-protect address sequence follows:
1. Read address 24555h
2. Read address 3AAAAh
3. Read address 02333h
4. Read address 1CCCCh
5. Read address 000FFh
6. Read address 3EF00h
7. Write address 3AAAAh
8. Write address 1CCCCh
9. Write address 0FF00h
10.Read address 00000h
Note
If CE is LOw entering the sequence, then an address of
00000h must precede 24555h.
The address sequence provides a secure way of modifying the
protection. The write-protect sequence has a one in 3 × 10
32
chance of randomly accessing exactly the first six addresses.
The odds are further reduced by requiring three more write
cycles, one that requires an exact inversion of the data byte.
Figure 2 on page 6
shows a flow chart of the entire write-protect
operation. The write-protect settings are nonvolatile. The factory
default: all blocks are unprotected.
For example, the following sequence write-protects addresses
from 18000h to 27FFFh (sectors 3 and 4):
Address
Read
Read
Read
Read
Read
Read
Write
Write
Write
Read
24555h
3AAAAh
02333h
1CCCCh
000FFh
3EF00h
3AAAAh
1CCCCh
0FF00h
00000h
Data
–
–
–
–
–
–
18h; bits 3 and 4 = 1
E7h; complement of 18h
Don’t care
Document Number: 001-86190 Rev. *F
Page 5 of 22
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