US1010
1A LOW DROPOUT POSITIVE
ADJUSTABLE REGULATOR
FEATURES
Guaranteed < 1.3V Dropout at Full Load
Current
Fast Transient Response
1% Voltage Reference Initial Accuracy
Built-in Thermal Shutdown
Available in SOT-223, D-PAK , Power Flex
and 8 pin SOIC Surface Mount Packages
DESCRIPTION
PRELIMINARY DATASHEET
APPLICATIONS
VGA & Sound Card Applications
Low Voltage High Speed Termination Applications
Standard 3.3V Chip-Set and Logic Applications
The US1010 is a low dropout three terminal adjustable
regulator with minimum of 1A output current capability.
This product is specifically designed to provide well regu-
lated supply for low voltage IC applications such as
high
speed bus termination and low current 3.3V logic
supply.
The US1010 is also well suited for other appli-
cations such as VGA and sound cards. The US 1010 is
guaranteed to have <1.3V drop out at full load cur-
rent
making it ideal to provide well regulated outputs of
2.5V to 3.6V with 4.75V to 7V input supply.
TYPICAL APPLICATION
D1
5V
C1
10uF
Vin
3
2
R1
121
US1010
Vout
2.85V / 1A
C2
22uF
Adj
1010app1-1.4
1
R2
154
Typical Application of US1010 in a 5V to 2.85V SCSI termination regulator .
PACKAGE ORDER INFORMATION
Tj (°C)
0 TO 150
2 PIN PLASTIC
TO252 (D)
US1010CD
3 PIN PLASTIC
SOT223 (Y)
US1010CY
2 PIN PLASTIC
POWER FLEX (P)
US1010CP
8 PIN PLASTIC
SOIC (S)
US1010CS
Rev. 1.3
10/30/00
2-1
US1010
ABSOLUTE MAXIMUM RATINGS
Input Voltage (Vin) .................................................................. 7V
Power Dissipation ............................................ Internally Limited
Storage Temperature Range .............................. -65
°
C TO 150
°
C
Operating Junction Temperature Range .................. 0
°
C TO 150
°
C
PACKAGE INFORMATION
2 PIN PLASTIC TO252 ( D )
FRONT VIEW
3
3 PIN PLASTIC SOT223 ( Y )
TOP VIEW
2 PIN PLASTIC PFLEX ( P )
FRONT VIEW
8 PIN PLASTIC SOIC (S)
TOP VIEW
Vin
3
Vin
Vout
Adj
Tab is
Vout
4
3
Vin
Tab is
Vout
4
Tab is
Vout
1
2
1
Adj
1
Adj
Vin
NC
NC
Adj
1
2
3
4
8
7
6
5
Vout
Vout
Vout
Vout
θ
JA
=70°C/W for 0.5" Sq pad
θ
JA
=90°C/W for 0.4" Sq pad
θ
JA
=70°C/W for 0.5" Sq pad
θ
JA
=55°C/W for 1" Sq pad
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over, Cin=1uF, Cout=10uF, and Tj=0 to 150
°
C.Typical
values refer to Tj=25
°
C.
PARAMETER
Reference Voltage
Line Regulation
Load Regulation (note 1)
Dropout Voltage
(note 2)
Current Limit
Minimum Load Current
(note 3)
Thermal Regulation
Ripple Rejection
Adjust Pin Current
Adjust Pin Current Change
Temperature Stability
Long Term Stability
RMS Output Noise
SYM
V
REF
TEST CONDITION
MIN
TYP
Io=10mA,Tj=25
°
C,(Vin-Vo)=1.5V 1.243 1.250
Io=10mA, (Vin-Vo)=1.5V
1.237 1.250
Io=10mA,1.3V<(Vin-Vo)<7V
Vin=3.3V,Vadj=0,10mA<Io<1A
Note 2 , Io=1A
Vin=3.3V,dVo=100mV
Vin=3.3V,Vadj=0V
30 mS PULSE,Vin-Vo=3V,Io=1A
f=120HZ ,Co=25uF Tan
Io=0.5A,Vin-Vo=3V
Io=10mA,Vin-Vo=1.5V,Tj=25
Io=10mA,Vin-Vo=1.5V
Io=10mA,Vin-Vo=1.5V,Tj=25
Vin=3.3V,Vadj=0V,Io=10mA
Tj=125
°
C,1000 Hrs
Tj=25
°
C 10hz<f<10khz
1.1
1.1
5
0.01
60
70
55
0.2
0.5
0.3
0.003
120
5
1
10
0.02
MAX
1.257
1.263
0.2
0.4
1.3
UNITS
V
%
%
V
A
mA
%/W
dB
uA
uA
%
%
%Vo
∆V
O
I
ADJ
Note 1 :
Low duty cycle pulse testing with Kelvin con-
nections are required in order to maintain accurate data.
Note 2 :
Drop-out voltage is defined as the minimum
differential voltage between Vin and Vout required to main-
tain regulation at Vout. It is measured when the output
voltage drops 1% below its nominal value.
Note 3 :
Minimum load current is defined as the mini-
mum current required at the output in order for the out-
put voltage to maintain regulation. Typically the resistor
dividers are selected such that it automatically main-
tains this current.
2-2
Rev. 1.3
10/30/00
US1010
PIN DESCRIPTIONS
PIN #
1
2
3
PIN SYMBOL
Adj
Vout
Vin
PIN DESCRIPTION
A resistor divider from this pin to the Vout pin and ground sets the output voltage.
The output of the regulator. A minimum of 10uF capacitor must be connected
from this pin to ground to insure stability.
The input pin of the regulator. Typically a large storage capacitor is connected
from this pin to ground to insure that the input voltage does not sag below the
minimum drop out voltage during the load transient response. This pin must
always be 1.3V higher than Vout in order for the device to regulate properly.
BLOCK DIAGRAM
Vin 3
2 Vout
+
+
1.25V
CURRENT
LIMIT
THERMAL
SHUTDOWN
1 Adj
1010blk1-1.0
Figure 1 - Simplified block diagram of the US1010
APPLICATION INFORMATION
Introduction
The US1010 adjustable Low Dropout (LDO) regulator is
a 3 terminal device which can easily be programmed
with the addition of two external resistors to any volt-
ages within the range of 1.25 to 5.5 V.This regulator
unlike the first generation of the 3T regulators such as
LM117 that required 3V differential between the input
and the regulated output,only needs 1.3V differential to
maintain output regulation. This is a key requirement for
today’slow voltage IC applications that typically need
3.3V supply and are often generated from the 5V sup-
ply. Other applications such as high speed memory ter-
mination need to switch the load current from zero to full
load in tens of nanoseconds at the their pins ,which
translates to an approximately 300 to 500 nS current
step at the regulator . In addition, the output voltage tol-
erances are sometimes tight and they include the tran-
sient response as part of the specification.
The US1010 is specifically designed to meet the fast
current transient needs as well as providing an accurate
initial voltage , reducing the overall system cost with the
need for fewer output capacitors.
Rev. 1.3
10/30/00
2-3
US1010
Output Voltage Setting
The US1010 can be programmed to any voltages in the
range of 1.25V to 5.5V with the addition of R1 and R2
external resistors according to the following formula:
R
2
V
OUT
=
V
REF
1
+ +
I
ADJ
×
R
2
R
1
Where : V
REF
= 125 V Typically
.
I
ADJ
= 50 uA Typically
R
1
& R
2
as shown in figure 2
regulation is achieved when the bottom side of R2 is
connected to the load and the top side of R1 resistor is
connected directly to the case or the Vout pin of the
regulator and not to the load. In fact , if R1 is connected
to the load side, the effective resistance between the
regulator and the load is gained up by the factor of (1+R2/
R1) ,or the effective resistance will be ,Rp(eff)=Rp*(1+R2/
R1).It is important to note that for high current applica-
tions, this can represent a significant percentage of the
overall load regulation and one must keep the path from
the regulator to the load as short as possible to mini-
mize this effect.
Vin
Vin
Vout
Vout
Vin
Vref
R1
Vin
Vout
PARASITIC LINE
RESISTANCE
US1010
Adj
Rp
US1010
Adj
R1
RL
IAdj = 50uA
R2
1010app2-1.0
R2
Figure 2 - Typical application of the US1010
for programming the output voltage.
The US1010 keeps a constant 1.25V between the out-
put pin and the adjust pin. By placing a resistor R1 across
these two pins a constant current flows through R1, add-
ing to the Iadj current and into the R2 resistor producing
a voltage equal to the (1.25/R1)*R2 +
I
adj*R2 which will
be added to the 1.25V to set the output voltage. This is
summarized in the above equation. Since the minimum
load current requirement of the US1010 is 10 mA , R1 is
typically selected to be 121
Ω
resistor so that it auto-
matically satisfies the minimum current requirement.
Notice that since Iadj is typically in the range of 50uA it
only adds a small error to the output voltage and should
only be considered when a very precise output voltage
setting is required. For example, in a typical 3.3V appli-
cation where R1=121
Ω
and R2=200
Ω
the error due to
Iadj is only 0.3% of the nominal set point.
1010app3-1.0
Figure 3 - Schematic showing connection for best load
regulation
Stability
The US1010 requires the use of an output capacitor as
part of the frequency compensation in order to make the
regulator stable. Typical designs for microprocessor ap-
plications use standard electrolytic capacitors with a
typical ESR in the range of 50 to 100 m
Ω
and an output
capacitance of 500 to 1000uF. Fortunately as the ca-
pacitance increases, the ESR decreases resulting in a
fixed RC time constant. The US1010 takes advantage of
this phenomena in making the overall regulator loop
stable.For most applications a minimum of 100uF alu-
minum electrolytic capacitor such as Sanyo MVGX se-
ries ,Panasonic FA series as well as the Nichicon PL
series insures both stability and good transient response.
Load Regulation
Since the US1010 is only a 3 terminal device , it is not
possible to provide true remote sensing of the output
voltage at the load.Figure 3 shows that the best load
2-4
Rev. 1.3
10/30/00
US1010
Thermal Design
The US1010 incorporates an internal thermal shutdown
that protects the device when the junction temperature
exceeds the maximum allowable junction temperature.
Although this device can operate with junction tempera-
tures in the range of 150
°
C ,it is recommended that the
selected heat sink be chosen such that during maxi-
mum continuous load operation the junction tempera-
ture is kept below this number. The example below for
a SCSI terminator application shows the steps in se-
lecting the proper regulator in a surface mount pack-
age .(See US1015 for non surface mount packages)
Assuming the following specifications :
V
IN
=
5 V
V
F
=
0.5 V
V
O
=
2.85V
I
OUT
MAX
=
0.8 A
T
A
=
35
°
C
Where ; V
F
is the forward voltage drop of the D1diode
as shown in figure 4.
The steps for selecting the right package with proper
board area for heatsinking to keep the junction tem-
perature below 135
°
C is given as :
1) Calculate the maximum power dissipation using :
P
D
=
0.8
×
(
5
−
0.5
−
2.85
)
=
132 W
.
2) Calculate the maximum
θ
JA
allowed for our ex-
ample:
T
J
−
T
A
P
D
135
−
35
=
75.6
°
C / W
θ
JA
MAX
=
132
.
θ
JA
MAX
=
2) Select a package from the datasheet with lower
θ
JA
than the one calculated in the previous step.
Selecting TO252 (D Pak) with at least 0.5" square of
0.062" FR4 board using 1OZ copper has 70
°
C/W
which is lower than the calculated number.
P
D
=
I
OUT
×
(
V
IN
−
V
F
−
V
OUT
)
To set the output DC voltage, we need to select R1 and
R2 :
3) Assuming
R1=121
Ω
, 1%
V
OUT
2.85
R
2
=
−
1
×
121
=
−
1
×
121
=
154.8
Ω
V
REF
125
.
Select
R2=154
Ω
,1%
D1
5V
C1
10uF
Vin
Vout
2.85V
C2
22uF
R1
121
1%
R2
154
1%
US1010
Adj
1010app4-1.3
Figure 4 - Final Schematic for half of the
GTL+ termination regulator.
Layout Consideration
The output capacitors must be located as close to
the Vout
terminal of the device as possible. It is recom-
mended to use a section of a layer of the PC board as a
plane to connect the Vout pin to the output capacitors to
prevent any high frequency oscillation that may result
due to excessive trace inductance.
Rev. 1.3
10/30/00
2-5
FPGA/CPLD
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