US3012/3012A
5 BIT PROGRAMMABLE SYNCHRONOUS BUCK
CONTROLLER IC
PRELIMINARY DATASHEET
FEATURES
Dual Layout Compatible with RC5051
Designed to meet Intel specification of VRM8.2
& VRM8.3 for Pentium II™
On board DAC programs the output voltage
from 1.3V to 3.5V (US3010) & 1.8V to 3.5V for
US3010A
Loss less Short Circuit Protection
Synchronous operation allows maximum
efficiency
Patented architecture allows fixed frequency
operation as well as 100% duty cycle during
dynamic load
Soft Start
High current totem pole driver for direct
driving of the external Power MOSFET
Power Good function
DESCRIPTION
The US3012 family of controller ICs are specifically de-
signed to meet Intel specification for Pentium II™ and
Pentium Pro™ microprocessor applications as well as
the next generation P6 family processors. These prod-
ucts feature a patented topology that in combination
with a few external components as shown in the typical
application circuit below ,will provide in excess of 16A
of output current for an on- board DC/DC converter while
automatically providing the right output voltage via the 5
bit internal DAC .These devices also feature,
loss less
current sensing by using the Rds-on of the high side
Power MOSFET as the sensing resistor,
a Power Good
window comparator that switches its open collector out-
put low when the output is outside of a
±10%
window .
Other features of the device are ; Undervoltage lockout
for both 5V and 12V supplies as well as an external
programmable soft start function as well as program-
ming the oscillator frequency by using an external ca-
pacitor.
APPLICATIONS
Pentium II & Pentium Pro™ processor DC to DC
converter application
Low cost Pentium with AGP
TYPICAL APPLICATION
L1
L2
Q1
C5
C1
C3
R3
R5
Q2
R6
R2
R4
C7
C11
R7
R8
R9
5V
C4
C6
R10
R1
D1
R11
14
Vfb/
GndD
En 2
R12
R13
12V
13
V12
7 NC/Vccp
6
V5
4
CS+
12
HDrv
5
CS-
9
LDrv
10
Gnd
OutEn
Power Good
C9
C10
US3012
16 SS/Vref
C2
D4
8
D3
17
D2
18
D1
19
D0
20
NC/
GndP
11
NC/
GndA
15
PGd 3
Ct
1
C8
VID4
VID3
VID2
VID1
3012app1-1.1
VID0
Notes: Pentium II and Pentium Pro are
trade marks of Intel Corp.
PACKAGE ORDER INFORMATION
Ta (°C)
0 TO 70
0 TO 70
Rev. 1.0
5/6/98
Device
US3012CW
US3012ACW
Package
20 pin Plastic SOIC WB
20 pin Plastic SOIC WB
VID Voltage Range
1.3V to 3.5V
1.8V to 3.5V
4-1
US3012/3012A
ABSOLUTE MAXIMUM RATINGS
V5 supply Voltage ........................................... 7V
V12 Supply Voltage ............................................ 20V
Storage Temperature Range ................................. -65 TO 150
°
C
Operating Junction Temperature Range .......... 0 TO 125
°
C
PACKAGE INFORMATION
20 PIN WIDE BODY PLASTIC SOIC (W)
TOP VIEW
Ct
1
En
2
PGd
3
CS+
4
CS-
5
V5
6
NC
7
D4
8
LDrv
9
PGnd
10
20
D0
19
D1
18
D2
17
D3
16
SS
15
Gnd
14
Vfb
13
V12
12
HDrv
11
NC
θ
JA
=85°C/W
ELECTRICAL SPECIFICATIONS
Unless otherwise specified ,these specifications apply over ,V12 = 12V, V5 = 5V and Ta=0 to 70°C. Typical values
refer to Ta =25°C. Low duty cycle pulse testing are used which keeps junction and case temperatures equal to the
ambient temperature.
PARAMETER
SYM TEST CONDITION
VID Section
DAC output voltage
(note 1)
DAC Output Line Regulation
DAC Output Temp Variation
VID Input LO
VID Input HI
VID input internal pull-up
resistor to V5
Power Good Section
Under voltage lower trip point
Vout ramping down
Under voltage upper trip point
Vout ramping up
UV Hysterises
Over voltage upper trip point
Vout ramping up
Over voltage lower trip point
Vout ramping down
OV Hysterises
Power Good Output LO
RL=3mA
Power Good Output HI
RL=5K pull up to 5V
Soft Start Section
Soft Start Current
CS+ =0V , CS- =5V
MIN
0.99Vs
TYP
Vs
MAX
1.01Vs
0.1
0.5
0.4
2
27
UNITS
V
%
%
V
V
kΩ
0.89Vs
.015Vs
1.09Vs
.015Vs
4.8
0.90Vs
0.92Vs
.02Vs
1.10Vs
1.08Vs
.02Vs
0.91Vs
.025Vs
1.11Vs
.025Vs
0.4
V
V
V
V
V
V
V
V
uA
10
4-2
Rev. 1.0
5/6/98
US3012/3012A
UVLO Section
UVLO Threshold-12V
UVLO Hysterises-12V
UVLO Threshold-5V
UVLO Hysterises-5V
Error Comparator Section
Input bias current
Input Offset Voltage
Delay to Output
Current Limit Section
C.S Threshold Set Current
C.S Comp Offset Voltage
Hiccup Duty Cycle
Supply Current
Operating Supply Current
Supply ramping up
Supply ramping up
9.2
0.3
4.1
0.2
10
0.4
4.3
0.3
10.8
0.5
4.5
0.4
2
+2
100
200
240
+5
2
V
V
V
V
uA
mV
nS
uA
mV
%
-2
Vdiff=10mV
160
-5
Css=0.1 uF
CL=3000pF
V5
V12
CL=3000pF
CL=3000pF
CL=3000pF
Ct=150pF
20
14
70
70
200
220
V5
35
2
0.8
100
130
300
250
0.2
mA
nS
nS
nS
Khz
V
V
kΩ
V
V
Output Drivers Section
Rise Time
Fall Time
Dead band Time
Oscillator Section
Osc Frequency
Osc Valley
Osc Peak
Output Enable Section
Pull up Resistor to V5
HI Threshold Voltage
LO Threshold Voltage
100
190
Note 1: Vs refers to the set point voltage given in Table 1.
D4
D3
D2
D1
D0
Vs
D4
D3
D2
0
1
1
1
1
1.30*
1
1
1
0
1
1
1
0
1.35*
1
1
1
0
1
1
0
1
1.40*
1
1
1
0
1
1
0
0
1.45*
1
1
1
0
1
0
1
1
1.50*
1
1
0
0
1
0
1
0
1.55*
1
1
0
0
1
0
0
1
1.60*
1
1
0
0
1
0
0
0
1.65*
1
1
0
0
0
1
1
1
1.70*
1
0
1
0
0
1
1
0
1.75*
1
0
1
0
0
1
0
1
1.80
1
0
1
0
0
1
0
0
1.85
1
0
1
0
0
0
1
1
1.90
1
0
0
0
0
0
1
0
1.95
1
0
0
0
0
0
0
1
2.00
1
0
0
0
0
0
0
0
2.05
1
0
0
* Output voltage is disabled for US3012A.
** Output voltage is disabled for all versions.
Table 1 - Set point voltage vs. VID codes
D1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
D0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Vs
**
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
Rev. 1.0
5/6/98
4-3
US3012/3012A
PIN DESCRIPTIONS
PIN# PIN SYMBOL
20
D0
19
18
17
8
3
D1
D2
D3
D4
PGd
Pin Description
LSB input to the DAC that programs the output voltage. This pin can be pulled up exter-
nally by a 10k resistor to either 3.3V or 5V supply.
Input to the DAC that programs the output voltage.This pin can be pulled up externally by
a 10kΩ resistor to either 3.3V or 5V supply.
Input to the DAC that programs the output voltage.This pin can be pulled up externally by
a 10k resistor to either 3.3V or 5V supply.
MSB input to the DAC that programs the output voltage.This pin can be pulled up exter-
nally by a 10k resistor to either 3.3V or 5V supply.
This pin selects a range of output voltages for the DAC. The voltage range for both the "A"
and the none "A" versions of the device is given in table 1.
This pin is an open collector output that switches LO when the output of the converter is
not within
±10%
(typ) of the nominal output voltage.When PWRGD pin switches LO the
sat voltage is less than 0.4V at 3mA.
This pin is connected directly to the output of the Core supply to provide feedback to the
Error comparator.
This pin is connected to the Drain of the power MOSFET of the Core supply and it
provides the positive sensing for the internal current sensing circuitry. An external resis-
tor programs the C.S threshold depending on the Rds of the power MOSFET. An external
capacitor is placed in parallel with the programming resistor to provide high frequency
noise filtering.
This pin is connected to the Source of the power MOSFET for the Core supply and it
provides the negative sensing for the internal current sensing circuitry.
This pin provides the soft start for the switching regulator. An internal current source
charges an external capacitor that is conected from this pin to the GND which ramps up
the outputs of the switching regulator, preventing the outputs from overshooting as wellas
limiting the input current. The second function of the Soft Start cap is to provide long off
time for the synchronous MOSFET or the Catch diode (HICCUP) during current limiting.
This pin programs the oscillator frequency in the range of 50 kHZ to 500kHZ with an
external capacitor connected from this pin to the GND.
This pin serves as the ground pin and must be conected directly to the ground plane. A
high frequency capacitor (0.1 to 1 uF) must be connected from V5 and V12 pins to this
pin for noise free operation.
Output driver for the synchronous power MOSFET.
Output driver for the high side power MOSFET.
This pin is connected to the 12 V supply and serves as the power Vcc pin for the output
drivers.A high frequency capacitor (0.1 to 1 uF) must be connected directly from this pin
to GND pin in order to supply the peak current to the power MOSFET during the transi-
tions.
5V supply voltage.
This is the output enable pin.This pin is internally pulled high through a resistor to 5V
supply. A low signal on this pin disables the output.
No connect.
14
4
Vfb
CS+
5
16
CS-
SS
1
10
Ct
Gnd
9
12
13
LDrv
HDrv
V12
6
2
7,11
15
V5
OUTEN
N.C
4-4
Rev. 1.0
5/6/98
US3012/3012A
BLOCK DIAGRAM
Vfb
En
V12
UVLO
V5
+
Vset
Enable
Vset
Enable
V12
HDrv
PWM
Control
V12
D0
D1
D2
D3
D4
5Bit
DAC,
Ctrl
Logic
Enable
Slope
Comp
LDrv
Osc
CS-
Over
Current
Soft
Start &
Fault
Logic
CS+
200uA
Enable
Ct
SS
1.1Vset
PGd
Gnd
0.9Vset
3012Ablk1-1.1
PGnd
Figure 1 - Simplified block diagram of the US3012/3012A.
Rev. 1.0
5/6/98
4-5
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