US3011
5 BIT PROGRAMMABLE SYNCHRONOUS BUCK
CONTROLLER IC
PRELIMINARY DATASHEET
FEATURES
Dual Layout Compatible with HIP6004A
Designed to meet Intel specification of VRM8.4
for Pentium III™
On board DAC programs the output voltage
from 1.3V to 3.5V. The US3011 remains on for
VID code of (11111).
Loss less Short Circuit Protection
Synchronous operation allows maximum
efficiency
Patented architecture allows fixed frequency
operation as well as 100% duty cycle during
dynamic load
Over Voltage Protection Output
Soft Start
High current totem pole driver for direct
driving of the external Power MOSFET
Power Good function
DESCRIPTION
The US3011controller IC is specifically designed to meet
Intel specification for latest Pentium III™ microproces-
sor applications as well as the next generation P6 fam-
ily processors. These products feature a patented topol-
ogy that in combination with a few external components
as shown in the typical application circuit ,will provide in
excess of 20A of output current for an on- board DC/DC
converter while automatically providing the right output
voltage via the 5 bit internal DAC.These devices also
features,
loss less current sensing by using the Rds-
on of the high side Power MOSFET as the sensing
resistor,
a Power Good window comparator that switches
its open collector output low when the output is outside
of a
±10%
window and an OVP output. Other features of
the device are ; Undervoltage lockout for both 5V and
12V supplies , an external programmable soft start func-
tion as well as programming the oscillator frequency by
using an external capacitor.
APPLICATIONS
Pentium III & Pentium II™ processor DC to DC con-
verter application
Low cost Pentium with AGP
TYPICAL APPLICATION
L1
L2
Q1
5V
C5
C1
C3
R2
R1
C8
Q2
R3
R4
C10
C6
C11
D1
C4
R7
18
V12
11 NC/Gnd
2
CS+
14
HDrv
15
NC/
Boot
13
CS-
17
LDrv
16
Gnd
1
NC/Sen
Vfb 10
R5
V5/Comp 9
D3
7
D2
6
D1
5
D0
4
Ct/Rt
20
OVP
19
PGd
12
C9
R6
R8
12V
R9
C12
C13
US3011
3 SS
C2
D4
8
VID4
VID3
VID2
VID1
VID0
C7
Power Good
C14
3011app1-1.1
OVP
Notes: Pentium II and Pentium III are
trade marks of Intel Corp.
PACKAGE ORDER INFORMATION
Ta (°C)
0 TO 70
Device
US3011CW
Package
20 pin Plastic SOIC WB
VID Voltage Range
1.3V to 3.5V
Rev. 1.3
12/8/00
4-1
US3011
ABSOLUTE MAXIMUM RATINGS
V5 supply Voltage ........................................... 7V
V12 Supply Voltage ............................................ 20V
Storage Temperature Range ................................. -65 TO 150
°
C
Operating Junction Temperature Range .......... 0 TO 125
°
C
PACKAGE INFORMATION
20 PIN WIDE BODY PLASTIC SOIC (W)
TOP VIEW
NC
1
CS+
2
SS
3
D0
4
D1
5
D2
6
D3
7
D4
8
V5
9
Vfb
10
20
Ct
19
OVP
18
V12
17
LDrv
16
Gnd
15
NC
14
HDrv
13
CS-
12
PGd
11
NC
θ
JA
=85°C/W
Unless otherwise specified ,these specifications apply over ,V
12
= 12V, V
5
= 5V and Ta=0 to 70
°
C. Typical values
refer to Ta =25
°
C. Low duty cycle pulse testing are used which keeps junction and case temperatures equal to the
ambient temperature.
PARAMETER
SYM TEST CONDITION
VID Section
DAC output voltage
(note 1)
DAC Output Line Regulation
DAC Output Temp Variation
VID Input LO
VID Input HI
VID input internal pull-up
resistor to V5
Power Good Section
Under voltage lower trip point
Vout ramping down
Under voltage upper trip point
Vout ramping up
UV Hysterises
Over voltage upper trip point
Vout ramping up
Over voltage lower trip point
Vout ramping down
OV Hysterises
Power Good Output LO
RL=3mA
Power Good Output HI
RL=5K pull up to 5V
Soft Start Section
Soft Start Current
CS+ =0V , CS- =5V
MIN
0.99Vs
TYP
Vs
MAX
1.01Vs
0.1
0.5
0.4
2
27
UNITS
V
%
%
V
V
kΩ
ELECTRICAL SPECIFICATIONS
0.89Vs
.015Vs
1.09Vs
.015Vs
4.8
0.90Vs
0.92Vs
.02Vs
1.10Vs
1.08Vs
.02Vs
0.91Vs
.025Vs
1.11Vs
.025Vs
0.4
V
V
V
V
V
V
V
V
uA
10
4-2
Rev. 1.3
12/8/00
US3011
UVLO Section
UVLO Threshold-12V
UVLO Hysterises-12V
UVLO Threshold-5V
UVLO Hysterises-5V
Error Comparator Section
Input bias current
Input Offset Voltage
Delay to Output
Current Limit Section
C.S Threshold Set Current
C.S Comp Offset Voltage
Hiccup Duty Cycle
Supply Current
Operating Supply Current
Supply ramping up
Supply ramping up
9.2
0.3
4.1
0.2
10
0.4
4.3
0.3
10.8
0.5
4.5
0.4
2
+2
100
200
240
+5
2
V
V
V
V
uA
mV
nS
uA
mV
%
-2
Vdiff=10mV
160
-5
Css=0.1 uF
CL=3000pF
V5
V12
CL=3000pF
CL=3000pF
CL=3000pF
Ct=150pF
20
14
70
70
200
220
V5
50
100
130
300
250
0.2
mA
nS
nS
nS
Khz
V
V
mA
Output Drivers Section
Rise Time
Fall Time
Dead band Time
Oscillator Section
Osc Frequency
Osc Valley
Osc Peak
Over Voltage Section
OVP Drive Current
100
190
Note 1: Vs refers to the set point voltage given in Table 1.
D4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
D2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
D1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
D0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Vs
1.30
1.35
1.40
1.45
1.50
1.55
1.60
1.65
1.70
1.75
1.80
1.85
1.90
1.95
2.00
2.05
D4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
D3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
D2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
D1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
D0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Vs
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
Table 1 - Set point voltage vs. VID codes
Rev. 1.3
12/8/00
4-3
US3011
PIN DESCRIPTIONS
PIN# PIN SYMBOL
4
D0
5
6
7
8
12
D1
D2
D3
D4
PGd
Pin Description
LSB input to the DAC that programs the output voltage. This pin can be pulled up exter-
nally by a 10k resistor to either 3.3V or 5V supply.
Input to the DAC that programs the output voltage.This pin can be pulled up externally by
a 10kΩ resistor to either 3.3V or 5V supply.
Input to the DAC that programs the output voltage.This pin can be pulled up externally by
a 10k resistor to either 3.3V or 5V supply.
MSB input to the DAC that programs the output voltage.This pin can be pulled up exter-
nally by a 10k resistor to either 3.3V or 5V supply.
This pin selects a range of output voltages for the DAC.
This pin is an open collector output that switches LO when the output of the converter is
not within
±10%
(typ) of the nominal output voltage.When PWRGD pin switches LO the
sat voltage is less than 0.4V at 3mA.
This pin is connected directly to the output of the Core supply to provide feedback to the
Error comparator.
This pin is connected to the Drain of the power MOSFET of the Core supply and it
provides the positive sensing for the internal current sensing circuitry. An external resis-
tor programs the C.S threshold depending on the Rds of the power MOSFET. An external
capacitor is placed in parallel with the programming resistor to provide high frequency
noise filtering.
This pin is connected to the Source of the power MOSFET for the Core supply and it
provides the negative sensing for the internal current sensing circuitry.
This pin provides the soft start for the switching regulator. An internal current source
charges an external capacitor that is conected from this pin to the GND which ramps up
the outputs of the switching regulator, preventing the outputs from overshooting as wellas
limiting the input current. The second function of the Soft Start cap is to provide long off
time for the synchronous MOSFET or the Catch diode (HICCUP) during current limiting.
This pin programs the oscillator frequency in the range of 50 kHZ to 500kHZ with an
external capacitor connected from this pin to the GND.
This pin serves as the ground pin and must be conected directly to the ground plane. A
high frequency capacitor (0.1 to 1 uF) must be connected from V5 and V12 pins to this
pin for noise free operation.
Output driver for the synchronous power MOSFET.
Output driver for the high side power MOSFET.
This pin is connected to the 12 V supply and serves as the power Vcc pin for the output
drivers.A high frequency capacitor (0.1 to 1 uF) must be connected directly from this pin
to GND pin in order to supply the peak current to the power MOSFET during the transi-
tions.
5V supply voltage.
Over voltage comparator output.
No connect
10
2
Vfb
CS+
13
3
CS-
SS
20
16
Ct
Gnd
17
14
18
LDrv
HDrv
V12
9
V5
19
OVP
15,11 NC
4-4
Rev. 1.3
12/8/00
US3011
BLOCK DIAGRAM
Vfb
Enable
V12
Vset
Enable
V12
UVLO
V5
+
Vset
HDrv
PWM
Control
V12
D0
D1
D2
D3
D4
5Bit
DAC,
Ctrl
Logic
Enable
Slope
Comp
LDrv
Osc
CS-
Over
Current
Soft
Start &
Fault
Logic
CS+
200uA
Enable
Ct
SS
1.18Vset
1.1Vset
OVP
PGd
Gnd
0.9Vset
3011Ablk1-1.1
Figure 1 - Simplified block diagram of the US3011.
Rev. 1.3
12/8/00
4-5
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