Product Specification
PE64102
General Description
The PE64102 is a DuNE™-enhanced Digitally Tunable
Capacitor (DTC) based on Peregrine’s UltraCMOS
®
technology. DTC products provide a monolithically
integrated impedance tuning solution for demanding
RF applications. They also offer a linear capacitance
change versus tuning state and excellent harmonic
performance compared to varactor-based tunable
solutions.
This highly versatile product can be mounted in series
or shunt configurations and uses a 3-wire (SPI
compatible) serial interface. It has a high ESD rating of
2 kV HBM on all ports making this the ultimate in
integration and ruggedness. The DTC will be offered in
a standard 12-lead 2.0 x 2.0 x 0.55 mm QFN
commercial package.
Peregrine’s DuNE™ technology enhancements deliver
high linearity and exceptional harmonics performance.
It is an innovative feature of the UltraCMOS
®
process,
providing performance superior to GaAs with the
economy and integration of conventional CMOS.
Figure 1. Functional Block Diagram
UltraCMOS
®
Digitally Tunable Capacitor
(DTC) 100 – 3000 MHz
Features
3-wire (SPI compatible) 8-bit serial interface
with built-in bias voltage generation and
stand-by mode for reduces power
consumption
DuNE
TM
-enhanced UltraCMOS
®
device
5-bit 32-state Digitally Tunable Capacitor
C = 1.88 pF – 14.0 pF (7.4:1 tuning ratio) in
discrete 391 fF steps
RF power handing (up to 26 dBm, 6 V
PK
RF)
and high linearity
High quality factor
Wide power supply range (2.3V to 3.6V) and
low current consumption
(typ. I
DD
= 30 µA @ 2.8V)
Optimized for shunt configuration, but can
also be used in series configuration
Excellent 2 kV HBM ESD tolerance on
all pins
Applications include:
Antenna tuning
Tunable filters
Phase shifters
Impedance matching
Figure 2. Package Type
12-lead 2 x 2 x 0.55 mm QFN
71-0066-01
Document No. DOC-25359-2
│
www.psemi.com
©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 13
PE64102
Product Specification
Table 1. Electrical Specifications @ 25°C, V
DD
= 2.8V
Parameter
Operating Frequency Range
7
Minimum Capacitance
Maximum Capacitance
Tuning Ratio
Step Size
Quality Factor (C
min
)
1
Configuration
Both
Shunt
6
Shunt
6
Shunt
6
Shunt
6
Shunt
6
State = 00000, 100 MHz (RF+ to Grounded RF-)
State = 11111, 100 MHz (RF+ to Grounded RF-)
C
max
/C
min
, 100 MHz
5 bits (32 states), constant step size (100 MHz)
470 – 582 MHz with L
s
removed
698 – 960 MHz, with L
s
removed
1710 – 2170 MHz, with L
s
removed
470 – 582 MHz with L
s
removed
698 – 960 MHz, with L
s
removed
1710 – 2170 MHz, with L
s
removed
State 00000
State 11111
470 – 582 MHz, Pin +26 dBm, 50Ω
698 – 915 MHz, Pin +26 dBm, 50Ω
1710 – 1910 MHz, Pin +26 dBm, 50Ω
470 – 582 MHz, Pin +20 dBm, 50Ω
698 – 915 MHz, Pin +20 dBm, 50Ω
1710 – 1910 MHz, Pin +20 dBm, 50Ω
IIP3 = (Pblocker + 2*Ptx - [IMD3]) / 2, where IMD3 = -95 dBm,
Ptx = +20 dBm and Pblocker = -15 dBm
State change to 10/90% delta capacitance between only two
states
Time from V
DD
within specification to all performances within
specification
State change from standby mode to RF state to all
performances within specification
60
2
5
5
10
20
20
Condition
Min
100
-10%
-10%
1.88
14.0
7.4:1
0.391
50
50
28
25
20
5
4.7
1.6
-36
-36
-36
-36
-36
-36
GHz
dBm
dBm
dBm
dBm
dBm
dBm
dBm
µs
µs
µs
pF
Typ
Max
3000
+10%
+10%
Unit
MHz
pF
pF
Quality Factor (C
max
)
1
Self Resonant Frequency
Shunt
6
Shunt
7
Shunt
6
Harmonics (2
fo
and 3
fo
)
4
Series
5
Shunt
6
Shunt
6
Shunt
6
Shunt
6
3rd Order Intercept Point
Switching Time
2, 3
Start-up Time
2
Wake-up Time
2,3
Note: 1. Q for a Shunt DTC based on a Series RLC equivalent circuit
Q = X
C
/ R = (X-X
L
) / R, where X = X
L
+ X
C
, X
L
= 2*pi*f*L, X
C
= -1 / (2*pi*f*C), which is equal to removing the effect of parasitic inductance L
S
2. DC path to ground at RF+ and RF– must be provided to achieve specified performance
3. State change activated on falling edge of SEN following data word
4. Between 50Ω ports in series or shunt configuration using a pulsed RF input with 4620 vs period, 50% duty cycle, measured per 3GPPTS45.005
5. In series configuration the greater RF power or higher RF voltage should be applied to RF+
6. RF
-
should be connected to ground
7. DTC operation above SRF is possible
©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 13
Document No. DOC-25359-2
│
UltraCMOS
®
RFIC Solutions
PE64102
Product Specification
Figure 3. Pin Configuration (Top View)
Pin 1
12
11
10
Table 3. Operating Ranges
1
Parameter
V
DD
Supply Voltage
I
DD
Power Supply Current
(Normal mode)
6
Symbol
V
DD
I
DD
I
DD
V
IH
V
IL
1.2
0
Min
2.3
Typ
2.8
30
20
Max
3.6
75
45
3.1
0.2
6
6
6
+26
+20
I
CTL
T
OP
T
ST
-40
-65
1
10
+85
+150
Units
V
µA
µA
V
V
V
PK
V
PK
V
PK
dBm
dBm
µA
°C
°C
SEN
11
13
GND
8
9 RF+
I
DD
Power Supply Current
(Standby mode)
2, 6
Control Voltage High
GND
22
33
8 GND
7
7 RF-
6
Control Voltage Low
Peak Operating RF Voltage
5
V
P
to V
M
V
P
to RFGND
V
M
to RFGND
RF Input Power (50Ω )
3, 4, 5
shunt
series
Input Control Current
SCLK
4
5
6
Table 2. Pin Descriptions
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
Pin Name
SEN
GND
SCLK
VDD
GND
RF-
RF-
GND
RF+
RF+
GND
SDAT
GND
Serial Enable
Digital and RF Ground
Serial Interface Clock Input
Power Voltage
Digital and RF Ground
Negative RF Port
1
Negative RF Port
1
Digital and RF Ground
3
Positive RF Port
2
Positive RF Port
2
Digital and RF Ground
Serial Interface Data Input
Digital and RF Ground
3
Description
Operating Temperature Range
Storage Temperature Range
Notes: 1. Operation should be restricted to the limits in the Operating Ranges table
2. The DTC is active when STBY is low (set to 0) and in low-current
stand-by mode when high (set to 1)
3. Maximum CW power available from a 50Ω source in shunt configuration
4. Maximum CW power available from a 50Ω source in series configuration
5. RF+ to RF- and RF+ and/or RF- to ground. Cannot exceed 6 V
PK
or max
RF input power (whichever occurs first)
6. I
DD
current typical value is based on V
DD
= 2.8V. Max I
DD
is based on
V
DD
= 3.6V
Table 4. Absolute Maximum Ratings
Symbol
V
DD
V
I
V
ESD
V
ESD
V
ESD
Parameter/Conditions
Power supply voltage
Voltage on any DC input
ESD Voltage (HBM, MIL_STD
883 Method 3015.7)
ESD Voltage (MM, JEDEC
JESD22-A115-A)
ESD Voltage (CDM, JEDEC
JESD22-C101)
Min
-0.3
-0.3
Max
4.0
4.0
2000
100
250
Units
V
V
V
V
V
Notes: 1. Pins 6 and 7 must be tied together on PCB board to reduce
inductance
2. Pins 9 and 10 must be tied together on PCB board to reduce
inductance
3. Pins 2, 5, 8, 11 and 13 must be connected together on PCB
Moisture Sensitivity Level
The Moisture Sensitivity Level rating for the
PE64102 in the 12-lead 2 x 2 mm QFN package is
MSL1.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS
®
devices are immune to latch-up.
Document No. DOC-25359-2
│
www.psemi.com
Exceeding absolute maximum ratings may cause
permanent damage. Operation between operating
range maximum and absolute maximum for
extended periods may reduce reliability.
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS
®
device, observe
the same precautions that you would use with other
ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the specified rating.
©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 3 of 13
PE64102
Product Specification
Performance Plots @ 25°C and 2.8V unless otherwise specified
Figure 4. Measured Shunt C (@ 100 MHz) vs
State (temperature)
Figure 5. Measured Shunt S
11
(major states)
Figure 6. Measured Step Size vs State
(frequency)
Figure 7. Measured Series S
11
/S
22
(major states)
Figure 8. Measured Shunt C vs
Frequency (major states)
Figure 9. Measured Series S
21
vs Frequency
(major states)
©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 4 of 13
Document No. DOC-25359-2
│
UltraCMOS
®
RFIC Solutions
PE64102
Product Specification
Figure 10. Measured Shunt Q vs
Frequency (major states)
Figure 11. Measured 2-Port Shunt S21 vs
Frequency (major states)
Figure 12. Measured Self Resonance
Frequency vs State
Figure 13. Measured Shunt Q vs State
160
140
120
100
80
60
40
20
0
5
10
15
State
20
25
30
Q
Measured Q vs. State
100 MHz
470 MHz
698 MHz
1710 MHz
Document No. DOC-25359-2
│
www.psemi.com
©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 5 of 13
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