SA828 Family
Three-Phase PWM Waveform Generator
DS4226 - 2.0 November 1996
The SA828 PWM generator has been designed to provide
waveforms for the control of variable speed AC machines,
uninterruptible power supplies and other forms of power
electronic devices which require pulse width modulation as a
means of efficient power control.
The six TTL level PWM outputs (Fig. 2) control the six
switches in a three-phase inverter bridge. This is usually via an
external isolation and amplification stage.
The SA828 is fabricated in CMOS for low power
consumption.
Information contained within the pulse width modulated
sequences controls the shape, power frequency, amplitude,
and rotational direction (as defined by the red-yellow-blue
phase sequence) of the output waveform. Parameters such as
the carrier frequency, minimum pulse width, and pulse delay
time may be defined during the initialisation of the device. The
pulse delay time (underlap) controls the delay between turning
on and off the two power switches in each output phase of the
inverter bridge, in order to accommodate variations in the turn-
on and turn-off times of families of power devices.
The SA828 is easily controlled by a microprocessor and its
fully-digital generation of PWM waveforms gives unprecedented
accuracy and temperature stability. Precision pulse shaping
capability allows optimum efficiency with any power circuitry.
The device operates as a stand-alone microprocessor
peripheral, reading the power waveform directly from an
internal ROM and requiring microprocessor intervention only
when operating parameters need to be changed.
An 8-bit multiplexed data bus is used to receive addresses and
data from the microprocessor/controller. This is a standard
MOTEL
TM
bus, compatible with most microprocessors/controllers.
Rotational frequency is defined to 12 bits for high accuracy
and a zero setting is included in order to implement DC
injection braking with no software overhead.
This family is pin and functionally compatible with the
MA828 PWM generator . Two standard wave shapes are
available to cover most applications. In addition, any
symmetrical wave shape can be integrated on-chip to order.
AD
3
AD
4
AD
5
AD
6
AD
7
WR* (R/W†)
RD* (DS†)
ALE* (AS†)
RST
CLK
CS
TRIP
RPHB
YPHB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
AD
2
AD
1
AD
0
VDD
ZPPB
ZPPY
ZPPR
WSS
RPHT
SET TRIP
YPHT
BPHT
V
SS
BPHB
SA828
21
20
19
18
17
16
15
DP28
*
= Intel bus format
† = Motorola bus format
AD
3
AD
4
AD
5
AD
6
AD
7
WR* (R/W†)
RD* (DS†)
ALE* (AS†)
RST
CLK
CS
TRIP
RPHB
YPHB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
AD
2
AD
1
AD
0
VDD
ZPPB
ZPPY
ZPPR
WSS
RPHT
SET TRIP
YPHT
BPHT
V
SS
BPHB
SA828
22
21
20
19
18
17
16
15
MP28
FEATURES
s
Fully Digital Operation
Fig. 1 Pin connections – top view (not to scale)
s
Interfaces with Most Microprocessors
s
Wide Power-Frequency Range
s
12-Bit Speed Control Accuracy
s
Carrier Frequency Selectable up to 24kHz
s
Waveform Stored in Internal ROM
s
Double Edged Regular Sampling
s
Selectable Minimum Pulse Width and Underlap Time
s
DC Injection Braking
ORDERING INFORMATION
SA8281/IG/DP1S
(28-lead DIL, sine + third harmonic
waveform)
SA8282/IG/DP1S
(28-lead DIL, sine waveform)
SA8281/IG/MP1S
(28-lead SOIC, Sine + third
harmonic waveform)
SA8382/IG/MP1S
(28-lead SOIC, sine waveform)
MOTEL is a registered Trademark of Intel Corp. and Motorola Corp.
SA828
ELECTRICAL CHARACTERISTICS
DC Characteristics
These characteristics are guaranteed over the following conditions (unless otherwise stated):
V
DD
= +5V
±5%,
T
AMB
= +25°C
Characteristic
Input high voltage
Input low voltage
Input leakage current
Output high voltage
Output low voltage
Supply current (static)
Supply current (dynamic)
Supply voltage
Symbol
V
IH
V
IL
I
IN
V
OH
V
OL
I
DD (static)
I
DD (dynamic)
V
DD
4·5
<10
5·0
4·0
>4·5
<0·2
0·4
100
20
5·5
Value
Min. Typ. Max.
2
0·8
10
V
V
µA
V
V
µA
mA
V
V
IN
= V
SS
or V
DD
I
OH
= – 12mA
I
OL
= 12mA
All outputs open circuit
f
CLK
= 10MHz
Units
Conditions
AC Characteristics
Characteristic
Clock frequency
Clock duty cycle
SET TRIP = 1
→
outputs tripped
→TRIP
= 0
Symbol
f
CLK
D
CLK
t
TRIP
40
Value
Typ. Max.
12·5
60
-
2/f
CLK
3/f
CLK
2/f
CLK
3/f
CLK
Units
MHz
%
µs
µs
Conditions
M : S ratio = 1 : 1
±20%
f
CLK
in MHz
f
CLK
in MHz
NOTE 1. For microprocessor interface timings, see Intel and Motorola bus timings (Tables 1 and 2).
ABSOLUTE MAXIMUM RATINGS
Supply voltage, V
DD
Voltage on any pin
Current through any I/O pin
Storage temperature
Operating temperature range
7V
V
SS
–0·3V to V
DD
+0·3V
±10mA
–65°C to +125°C
–40°C to +85°C
The temperature ranges quoted apply to all package types.
Many package types are available and extended temperature
ranges can be offered for some. Further information is available
on request.
Stresses above those listed in the Absolute Maximum
Ratings may cause permanent damage to the device. These
are stress ratings only and functional operation of the device at
these conditions, or at any other condition above those indicated
in the operations section of this specification, is not implied.
Exposure to Absolute Maximum Rating conditions for extended
periods may affect device reliability.
Pin
No.
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
PIN DESCRIPTIONS
Pin
No.
1
2
3
4
5
6
Name
AD
3
AD
4
AD
5
AD
6
AD
7
Intel:
WR
Motorola:
R/W
Intel:
RD
Motorola: DS
Intel: ALE
Motorola: AS
Type
I
I
I
I
I
I
Function
Multiplexed Address/Data
Multiplexed Address/Data
Multiplexed Address/Data
Multiplexed Address/Data
Multiplexed Address/Data(MSB)
Intel bus control: Write Strobe
Motorola bus control: Read/Write
select
Intel bus control: Read Strobe
Motorola bus control: Data Strobe
Intel bus control: Address Latch
Enable
Motorola bus control: Address
Strobe
Reset internal counters, active low
Clock input
Chip Select input, active low
Output trip status; low = output tripped
Name
RPHB
YPHB
BPHB
V
SS
BPHT
YPHT
SET TRIP
RPHT
WSS
ZPPR
ZPPY
ZPPB
V
DD
AD
0
AD
1
AD
2
Type
O
O
O
P
O
O
I
O
O
O
O
O
P
I
I
I
Function
Red Phase, Bottom power switch
Yellow Phase, Bottom power switch
Blue Phase, Bottom power switch
Negative power supply (0V)
Blue Phase, Top power switch
Yellow Phase, Top power switch
Set output trip. 120kΩ internal
pull-up resistor
Red Phase, Top power switch
Waveform Sampling Synchronisation
Zero Phase Pulse, Red phase
Zero Phase Pulse, Yellow phase
Zero Phase Pulse, Blue phase
Positive power supply
Multiplexed Address/Data (LSB)
Multiplexed Address/Data
Multiplexed Address/Data
7
8
I
I
9
10
11
12
RST
CLK
CS
TRIP
I
I
I
O
2
SA828
ZPP
O/Ps WSS
CS
MOTEL
INTERFACE
8
BUS
CONTROL
RED PHASE
PULSE
DELETION
PULSE
DELAY
CIRCUIT
RPHT
RPHB
SYSTEM
BUS
AD
0
-AD
7
BUS
DEMULTIPLEXER
R0
R1
R2
R3
R4
24-BIT
INITIALISATION
REGISTER
PHASING
AND
CONTROL
LOGIC
YELLOW PHASE
PULSE
DELETION
PULSE
DELAY
CIRCUIT
YPHT
YPHB
24-BIT
CONTROL
REGISTER
BLUE PHASE
RST
PULSE
DELETION
PULSE
DELAY
CIRCUIT
BPHT
BPHB
CLOCK
CLOCK
DIVIDER
ADDRESS
GENERATOR
TRIP
LATCH
TRIP
SET
TRIP
WAVEFORM
ROM
Fig. 2 SA828 internal block diagram
FUNCTIONAL DESCRIPTION
An asynchronous method of PWM generation is used with
uniform or ‘double-edged’ regular sampling of the waveform
stored in the internal ROM as illustrated in Fig. 3.
The triangle carrier wave frequency is selectable up to 24kHz
(assuming the maximum clock frequency of 12.5MHz is used),
enabling ultrasonic operation for noise critical applications. With
12.5MHz clock, power frequency ranges of up to 4kHz are
possible, with the actual output frequency resolved to 12-bit
accuracy within the chosen range in order to give precise motor
speed control and smooth frequency changing. The output phase
sequence of the PWM outputs can also be changed to allow both
forward and reverse motor operation.
PWM output pulses can be ‘tailored’ to the inverter
characteristics by defining the minimum allowable pulse width
(the SA828 will delete all shorter pulses from the ‘pure’ PWM pulse
train) and the pulse delay (underlap) time, without the need for
external circuitry. This gives cost advantages in both component
savings and in allowing the same PWM circuitry to be used for
control of a number of different motor drive circuits simply by
changing the microprocessor software.
Power frequency amplitude control is also provided with an
overmodulation option to assist in rapid motor braking. Alternatively,
braking may be implemented by setting the rotational speed to
0Hz. This is termed ‘DC injection braking’, in which the rotation of
the motor is opposed by allowing DC to flow in the windings.
A trip input allows the PWM outputs to be shut down immediately,
overriding the microprocessor control in the event of an emergency.
The Waveform Sampling Synchronisation (WSS) output may
be used in conjunction with the ZPP signals to provide feedback
of the actual rotational speed from the rotor. This is of particular
use in slip compensated systems.
Other possible SA828 applications are as a 3-phase waveform
generator as part of a switched-mode power supply (SMPS) or of
an uninterruptible power supply (UPS). In such applications the
high carrier frequency allows a very small switching transformer
to be used.
MICROPROCESSOR INTERFACE
The SA828 interfaces to the controlling microprocessor by
means of a multiplexed bus of the MOTEL format. This interface
bus has the ability to adapt itself automatically to the format and
timing of both MOTorola and IntEL interface buses (hence MOTEL).
Internally, the detection circuitry latches the status of the DS/RD
line when AS/ALE goes high. If the result is high then the Intel
mode is used; if the result is low then the Motorola mode is used.
This procedure is carried out each time that AS/ALE goes high. In
practice this mode selection is transparent to the user. For bus
connection and timing information refer to the description relevant
to the microprocessor/controller being used.
Industry standard microprocessors such as the 8085, 8088,
etc. and microcontrollers such as the 8051, 8052 and 6805 are all
compatible with the interface on the SA828. This interface consists
of 8 data lines, AD
0
- AD
7
(write-only in this instance), which are
multiplexed to carry both the address and data information, 3 bus
control lines, labelled
WR,RD
and ALE in Intel mode and R/W, DS
and AS in Motorola mode, and a Chip Select input,
CS,
which
allows the SA828 to share the same bus as other microprocessor
peripherals. It should be noted that all bus timings are derived from
the microprocessor and are independent of the SA828 clock
input.
3
SA828
TRIANGLE WAVE AT
CARRIER FREQUENCY,
SAMPLING ON
+VE
AND
–
VE PEAKS
PWM SWITCHING
INSTANTS
+1
0
POWER WAVEFORM
AS READ FROM
INTERNAL ROM
–
1
+1
RESULTING
PWM
WAVEFORM
0
–
1
Fig. 3 Asynchronous PWM generation with‘double-edged’ regular sampling as used by the SA828
t
1
ALE
AS
t
1
t
2
RD
t
4
t
3
t
5
t
7
t
2
WR
t
3
t
4
DS
t
6
t
8
t
9
R/W
CS
t
8
t
10
t
11
CS
t
9
AD
0
-AD
7
t
10
t
11
t
15
LATCH ADDRESS
t
12
LATCH DATA
AD
0
-AD
7
t
15
LATCH ADDRESS
t
12
LATCH DATA
Fig. 4 Intel bus timing definitions
Parameter
ALE high period
Delay time, ALE to
WR
WR
low period
Delay time,
WR
high to ALE high
CS
setup time
CS
hold time
Address setup time
Address hold time
Data setup time
Data hold time
Symbol
t
1
t
2
t
3
t
4
t
8
t
9
t
10
t
15
t
11
t
12
Min.
70
40
200
40
20
0
30
30
100
25
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Fig. 5 Motorola bus timing definitions
Parameter
AS high period
Delay time, as low to DS high
DS high period
Delay time, DS low to AS high
DS low period
DS high to R/W low setup time
R/W hold time
CS
setup time
CS
hold time
Address setup time
Address hold time
Write data setup time
Write data hold time
Symbol
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
15
t
11
t
12
Min.
90
40
210
40
200
10
10
20
0
30
30
110
30
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 1 Intel bus timings at V
DD
= 5V, T
AMB
=
+
25°C
Table 2 Motorola bus timings at V
DD
= 5V, T
AMB
= +25
°
C
4
SA828
MICROPROCESSOR BUS TIMING
Intel Mode (Fig. 4 and Table 1)
The address is latched by the falling edge of ALE. Data is
written from the bus into the SA828 on the rising edge of
WR.
RD
is not used in this mode because the registers in the SA828
are write only. However, this pin must be connected to
RD
(or
tied high) to enable the SA828 to select the correct interface
format.
Power frequency range
This sets the maximum power frequency that can be carried
within the PWM output waveforms. This would normally be set
to a value to prevent the motor system being operated outside
its design parameters.
Pulse delay time ('underlap')
For each phase of the PWM cycle there are two control
signals, one for the top switch connected to the positive
inverter DC supply and one for the bottom switch connected to
the negative inverter DC supply. In theory, the states of these
two switches are always complementary. However, due to the
finite and non-equal turn-on and turn- off times of power
devices, it is desirable when changing the state of the output
pair, to provide a short delay time during which both outputs
are off in order to avoid a short circuit through the switching
elements.
Pulse deletion time
A pure PWM sequence produces pulses which can vary in
width between 0% and 100% of the duty cycle. Therefore, in
theory, pulse widths can become infinitesimally narrow. In
practice this causes problems in the power switches due to
storage effects and therefore a minimum pulse width time is
required. All pulses shorter than the minimum specified are
deleted.
Counter reset
This facility allows the internal power frequency counter of
the SA828 to be set to zero, disabling the normal frequency
control and giving a 50% output duty cycle.
Motorola Mode (Fig. 5 and Table 2)
The address is latched on the falling edge of the AS line. Data
is written from the bus into the SA828 (only when R/W is low) on
the falling edge of DS (providing
CS is
low).
CONTROLLING THE SA828
The SA828 is controlled by loading data into two 24-bit
registers via the microprocessor interface. These registers are
the initialisation register and the control register.
The initialisation register would normally be loaded before
motor operation (i.e., prior to the PWM outputs being activated)
and sets up the basic operating parameters associated with the
motor and inverter. This data would not normally be updated
during motor operation.
The control register is used to control the PWM outputs (and
hence the motor) during operation e.g., stop/start, speed,
forward/reverse etc. and would normally be loaded and changed
only after the initialisation register has been loaded.
As the MOTEL bus interface is restricted to an 8-bit wide
format, data to be loaded into either of the 24-bit registers is first
written to three 8-bit temporary registers R0, R1 and R2 before
being transferred to the desired 24-bit register. The data is
accepted (and acted upon) only when transferred to one of the
24-bit registers.
Transfer of data from the temporary registers to either the
initialisation register or the control register is achieved by a write
instruction to a dummy register. Writing to dummy register R3
results in data transfer from R0, R1 and R2 to the control
register, while writing to dummy register R4 transfers data from
R0, R1 and R2 to the initialisation register. It does not matter
what data is written to the dummy registers R3 and R4 as they
are not real registers. It is merely the write instruction to either
of these registers which is acted upon in order to load the
initialisation and control registers.
AD
2
0
0
0
0
1
AD
1
0
0
1
1
0
AD
0
0
1
0
1
0
Register
R0
R1
R2
R3
R4
Comment
Temporary register R0
Temporary register R1
Temporary register R2
Transfers control data
Transfers initialisation data
Initialisation Register Programming
The initialisation register data is loaded in 8-bit segments into
the three 8-bit temporary registers R0-R2. When all the initialisation
data has been loaded into these registers it is transferred into the
24-bit initialisation register by writing to the dummy register R4.
FRS
2
FRS
1
FRS
0
X
X
CFS
2
CFS
2
CFS
2
FREQUENCY
RANGE
SELECT WORD
FRS
2
=
MSB
FRS
0
=
LSB
DON’T
CARE
Fig. 6 Temporary register R1
Carrier frequency selection
The carrier frequency is a function of the externally applied
clock frequency and a division ratio
n,
determined by the 3-bit
CFS word set during initialisation. The values of
n
are selected
as shown in Table 4.
CFS word
Value of n
101 100 011 010 001 000
32
16
8
4
2
1
Table 3 SA828 register addressing
Initialisation Register Function
The 24-bit initialisation register contains parameters which,
under normal operation, will be defined during the power-up
sequence. These parameters are particular to the drive circuitry
used, and therefore changing these parameters during a PWM
cycle is not recommended. Information in this register should
only be modified while
RST
is active (i.e. low) so that the PWM
outputs are inhibited (low) during the updating process.
The parameters set in the initialisation register are as follows:
Carrier frequency
Low carrier frequencies reduce switching losses whereas
high carrier frequencies increase waveform resolution and can
allow ultrasonic operation.
Table 4 Values of clock division ratio n
The carrier frequency,
f
CARR
,
is then given by:
k
f
CARR
=
512 x
n
where
k
= clock frequency and
n
= 1, 2, 4, 8, 16 or 32 (as set
by CFS)
Power frequency range selection
The power frequency range selected here defines the maximum
limit of the power frequency. The operating power frequency is
controlled by the 12-bit Power Frequency Select (PFS) word in
the control register but may not exceed the value set here.
CARRIER
FREQUENCY
SELECT WORD
CFS
2
=
MSB
CFS
0
=
LSB
5
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