®
®
T1/ESF Framer Circuit (ACCUNET T1.5)
ISO-CMOS ST-BUS™ FAMILY
MT8977
Preliminary Information
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
D3/D4 or ESF framing and SLC-96 compatible
Two frame elastic buffer with jitter tolerance
improved to 156 UI
Insertion and detection of A, B, C, D bits,
signalling freeze, optional debounce
Selectable B8ZS, jammed bit (ZCS) or no zero
code suppression
Yellow alarm and blue alarm signal capabilities
Bipolar violation count, F
T
error count, CRC
error count
Selectable robbed bit signalling
Frame and superframe sync. signals, Tx and Rx
AMI encoding and decoding
Per channel, overall, and remote loop around
Digital phase detector between T1 line and ST-
BUS
One uncommitted scan point and drive point
Pin compatible with MT8976 and MT8979
ST-BUS compatible
ISSUE 2
May 1995
Ordering Information
MT8977AC
28 Pin Ceramic DIP
MT8977AE
28 Pin Plastic DIP
MT8977AP
44 Pin PLCC
-40°C to 85°C
Description
The MT8977 is a variant of the MT8976 framer,
which has been enhanced to meet ACCUNET
®
T1.5
wander tolerance (138 UI).
The MT8977 meets ESF and D3/D4 formats, and is
compatible with SLC-96 systems.
Applications
•
•
•
DS1/ESF digital trunk interfaces
Computer to PBX interfaces (DMI and CPI)
High speed computer to computer data links
TxSF
C2i
F0i
RxSF
DSTo
DSTi
C1.5i
ST-BUS
Timing
Circuitry
2 Frame
Elastic Buffer
with Slip
Control
DS1
Link
Interface
2048-1544
Converter
RxFDLClk
RxFDL
RxA
Remote &
Digital
Loopbacks
RxB
TxA
TxB
TxFDLClk
TxFDL
RxD
Serial
Control
Interface
ABCD
Signalling RAM
E1.5i
Phase
Detector
DS1
Counter
Data
Interface
CSTi0
CSTi1
CSTo
XCtl
XSt
Control Logic
•
E8Ko
V
SS
V
DD
ACCUNET
®
T1.5 is a registered trademark of AT & T
Figure 1 - Functional Block Diagram
4-99
MT8977
ISO-CMOS
Preliminary Information
TxA
TxB
DSTo
NC
VSS
VDD
IC
NC
F0i
NC
E1.5i
28 PIN CERDIP/PDIP
Figure 2 - Pin Connections
Pin Description
Pin #
DIP
PLCC
Name
TxA
TxB
DSTo
NC
RxA
Description
Transmit A Output.
Unipolar output that can be used in conjunction with TxB and
external line driver circuitry to generate the bipolar DS1 signal.
Transmit B Output.
Unipolar output that can be used in conjunction with TxA
and external line driver circuitry to generate the bipolar DS1 signal.
Data ST-BUS Output.
A 2048 kbit/s serial output stream which contains the 24
PCM or data channels received from the DS1 line.
No Connection.
Receive A Complementary Input.
Accepts a unipolar split phase signal decoded
externally from the received DS1 bipolar signal. This input, in conjunction with
RxB, detects bipolar violations in the received signal.
Receive B Complementary Input.
Accepts a unipolar split phase signal
decoded externally from the received DS1 bipolar signal.
This input, in
conjunction with RxA, detects bipolar violations in the received signal.
Receive Data Input.
Unipolar RZ data signal decoded from the received DS1
signal. Generally the signals input at RxA and RxB are combined externally with a
NAND gate and the resulting composite signal is input at this pin.
Control ST-BUS Input #1.
per-channel control words.
A 2048 kbit/s serial control stream which carries 24
1
2
3
4
5
2
3
5
4
9
6
10
RxB
7
11
RxD
8
9
13
14
CSTi1
TxFDL
Transmit Facility Data Link (Input).
A 4 kHz serial input stream that is
multiplexed into the FDL position in the ESF mode, or the F
S
pattern when in SLC-
96 mode. It is clocked in on the rising edge of TxFDLClk.
Transmit Facility Data Link Clock (Output).
A 4 kHz clock used to clock in the
FDL data.
No connection.
10
11
16
TxFDLClk
NC
4-100
VSS
CSTi0
E8Ko
NC
VSS
XCtl
DSTi
RxFDLClk
CSTo
NC
XSt
44 PIN PLCC
TxA
TxB
DSTo
NC
RxA
RxB
RxD
CSTi1
TxFDL
TxFDLClk
NC
CSTi0
E8Ko
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
IC
F0i
E1.5i
C1.5i
RxSF
TxSF
C2i
RxFDL
DSTi
RxFDLClk
CSTo
XSt
XCtl
NC
NC
RxA
RxB
RxD
NC
CSTi1
TxFDL
NC
TxFDLClk
NC
6 5 4 3 2 1 44 43 42 41 40
7
39
8
38
9
37
10
36
11
35
12
34
13
33
14
32
15
31
16
30
29
17
18 19 20 21 22 23 24 25 26 27 28
C1.5i
RxSF
TxSF
NC
NC
C2i
NC
NC
NC
NC
RxFDL
Preliminary Information
Pin Description (Continued)
Pin #
DIP
PLCC
ISO-CMOS
MT8977
Name
CSTi0
E8Ko
Description
Control ST-BUS Input #0.
A 2048 kbit/s serial control stream that contains 24 per
channel control words and two master control words.
Extracted 8 kHz Output.
The E1.5i clock is internally divided by 193 to produce an
8 kHz clock which is aligned with the received DS1 frame and output at this pin. The
8 kHz signal is derived from C1.5 in Digital Loopback mode.
System Ground.
12
13
19
20
14
6,
18,
22
23
V
SS
15
XCtl
External Control (Output).
This is an uncommitted external output pin which is set
or reset via bit 3 in Master Control Word 1 on CSTi0. The state of XCtl is updated
once per frame.
External Status (Schmitt Trigger Input).
The state of this pin is sampled once per
frame and the status is reported in bit 5 of Master Status Word 2 on CSTo.
Control ST-BUS Output.
This is a 2048 kbit/s serial control stream which provides
the 24 per-channel status words, and two master status words.
Receive Facility Data Link Clock (Output).
A 4 kHz clock signal used to clock out
FDL information. The data is clocked out on the rising edge of RxFDLClk.
Data ST-BUS Input.
This pin accepts a 2048 kbit/s serial stream which contains the
24 PCM or data channels to be transmitted on the T1 trunk.
Received Facility Data Link (Output).
A 4 kHz serial output stream that is
demultiplexed from the FDL in ESF mode, or the received Fs bit pattern in SLC-96
mode. It is clocked out on the rising edge of RxFDLClk.
2.048 MHz Clock Input.
This is the master clock used for clocking serial data into
DSTi, CSTi0 and CSTi1. It is also used to clock serial data out of CSTo and DSTo.
Transmit Superframe Pulse Input.
A low going pulse applied at this pin will make
the next transmit frame the first frame of a superframe. The device will free run if
this pin is held high.
Received Superframe Pulse Output.
A pulse output on this pin designates that the
next frame of data on the ST-BUS is from frame 1 of the received superframe. The
period is 12 frames long in D3/D4 modes and 24 frames in ESF mode. Pulses are
output only when the device is synchronized to the received DS1 signal.
1.544 MHz Clock Input.
This is the DS1 transmit clock and is used to output data on
TxA and TxB. It must be phase-locked to C2i. Data is clocked out on the rising
edge of C1.5i.
1.544 MHz Extracted Clock (Input).
This clock which is extracted from the received
data is used to clock in data at RxA, RxB and RxD . The falling edge of the clock
is nominally aligned with the center of the received bit on RxD, RxA and RxB.
Frame Pulse Input.
This is the frame synchronization signal which defines the
beginning of the 32 channel ST-BUS frame.
Internal Connection.
Tied to V
SS
for normal operation
.
Positive Power Supply Input.
+5V
±5%.
16
17
18
19
20
24
26
27
28
29
XSt
CSTo
RxFDLClk
DSTi
RxFDL
21
22
34
37
C2i
TxSF
23
38
RxSF
24
39
C1.5i
25
40
E1.5i
26
27
28
42
44
1
F0i
IC
V
DD
4-101
MT8977
ISO-CMOS
Preliminary Information
Functional Timing Diagrams
125µSec
C2i
DSTi
DSTo
CSTi0/CSTi1
7
6
5
4
3
2
1
0
•
•
•
•
•
•
•
•
7
CSTo
7
6
5
4
3
2
1
0
•
•
•
•
•
•
•
•
7
Figure 3 - ST-BUS Timing
125µSec
E1.5i
INT DATA
1
1
0
0
1
1
0
1
DS1 AMI
LINE SIGNAL
RxA
RxB
RxD
E8Ko
Figure 4 - DS1 Receive Timing
C1.5i
INT DATA
TxA
TxB
DS1 AMI
LINE SIGNAL
Figure 5 - DS1 Transmit Timing
4-102
DSTi
0
X
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
1
2
3
4
X
5
6
7
8
X
9
10
11
12
X
13
14
15
16
X
17
18
19
20
X
21
22
23
24
X
25
26
27
28
X
29
30
31
DS1
1
2
3
4
24
ST-BUS CHANNEL VERSUS DS1 CHANNEL TRANSMITTED
6
7
8
X
7
8
9
10
11
12
13
14
15
16
17
18
19
20
9
10
11
12
X
13
14
15
16
X
17
18
19
20
X
21
22
23
24
X
25
26
27
28
X
21
29
30
31
DSTo
0
X
5
6
1
2
3
4
X
5
Preliminary Information
DS1
1
2
3
4
22
23
24
ST-BUS CHANNEL VERSUS DS1 CHANNEL RECEIVED
CSTi0
7
X
11
X
19
X
8
9
10
PC PC PC
CW CW CW
1
1
1
12
13
14
PC PC PC
CW CW CW
1
1
1
16
17
18
PC PC PC
CW CW CW
1
1
1
20
21
22
PC PC PC
CW CW CW
1
1
1
16
17
18
13
14
15
10
11
12
15
MC
W1
7
8
9
0
1
2
PC PC PC
CW CW CW
1
1
1
6
3
X
4
5
6
PC PC PC
CW CW CW
1
1
1
23
X
24
25
26
PC PC PC
CW CW CW
1
1
1
19
20
21
27
X
28
29
30
PC PC PC
CW CW CW
1
1
1
22
23
24
31
MC
W2
DS1
1
2
3
4
5
PCCW = Per Channel Control Word
MCW1/2 =Master Control Word 1/2
ST-BUS CHANNEL VERSUS DS1 CHANNEL CONTROLLED
CSTi1
7
X
8
9
10
PC PC PC
CW CW CW
2
2
2
11
X
15
X
7
8
9
10
11
12
13
14
12
13
14
PC PC PC
CW CW CW
2
2
2
0
1
2
PC PC PC
CW CW CW
2
2
2
6
3
X
4
5
6
PC PC PC
CW CW CW
2
2
2
16
17
18
PC PC PC
CW CW CW
2
2
2
15
19
X
20
21
22
PC PC PC
CW CW CW
2
2
2
16
17
18
23
X
24
25
26
PC PC PC
CW CW CW
2
2
2
19
20
21
27
X
28
29
30
PC PC PC
CW CW CW
2
2
2
22
23
24
31
X
DS1
1
2
3
4
5
PCCW = Per Channel Control Word
ST-BUS CHANNEL VERSUS DS1 CHANNEL CONTROLLED
7
X
11
X
7
8
9
8
9
10
PCS PCS PCS
W
W
W
10
15
12
13
14
16
17
18
MS PCS PCS PCS
PCS PCS PCS
W
W
W W1 W
W
W
11
12
13
14
15
19
X
20
21
22
PCS PCS PCS
W
W
W
16
17
18
23
X
24
25
26
PCS PCS PCS
W
W
W
19
20
21
27
X
31
28
29
30
PCS PCS PCS MS
W
W
W W2
22
23
24
ISO-CMOS
CSTo
3
0
1
2
4
5
6
PS PCS PCS PCS
PCS PCS PCS
W
W
W
W
W
W
W
6
DS1
1
2
3
4
5
PCSW =Per Channel Status Word
PSW = Phase Status Word
MSW =Master Status Word
X = Unused
ST-BUS VERSUS DS1 CHANNEL STATUS
Figure 6 - ST-BUS Channel Allocations
MT8977
4-103
PCB设计
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