MT88L85
®
3V Integrated DTMF Transceiver
with Power Down & Adaptive
Micro Interface
Advance Information
Features
•
•
•
•
•
•
•
•
•
External power down pin
Low voltage operation (2.7V - 3.6V)
Central office quality DTMF transmitter/
receiver
Low power consumption
High speed adaptive micro interface
Adjustable guard time
Automatic tone burst mode
Call progress tone detection to -30dBm
DTMF transmitter/receiver power down via
register control
ISSUE 1
May 1995
Ordering Information
MT88L85AE
MT88L85AN
MT88L85AP
-40°C to
24 Pin Plastic DIP
24 Pin SSOP
28 Pin PLCC
+85°C
Applications
•
•
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Credit card systems
Paging systems
Repeater systems/mobile radio
Interconnect dialers
Personal computers
The receiver section is based upon the industry
standard MT8870 DTMF receiver while the
transmitter utilizes a switched capacitor D/A
converter for low distortion, high accuracy DTMF
signalling. Internal counters provide a burst mode
such that tone bursts can be transmitted with precise
timing. A call progress filter can be selected allowing
a microprocessor to analyze call progress tones.
The MT88L85 utilizes an adaptive micro interface,
which allows the device to be connected to a number
of popular microcontrollers with minimal external
logic. The MT88L85 provides enhanced power down
features.
The transmitter and receiver may
independently be powered down via register
control. A full chip power down pin provides simple
power and control capability.
Description
The MT88L85 is a monolithic DTMF transceiver with
call progress filter.
It is fabricated in CMOS
technology offering low power consumption and high
reliability.
TONE
∑
D/A
Converters
Row and
Column
Counters
Transmit Data
Register
Status
Register
Data
Bus
Buffer
D0
D1
D2
D3
Tone Burst
Gating Cct.
IN+
IN-
GS
OSC1
OSC2
Oscillator
Circuit
Bias
Circuit
+
-
Dial
Tone
Filter
Control
Logic
Interrupt
Logic
IRQ/CP
High Group
Filter
Low Group
Filter
Control
Logic
Digital
Algorithm
and Code
Converter
Control
Register
A
Control
Register
B
I/O
Control
DS/RD
CS
R/W/WR
RS0
Steering
Logic
Receive Data
Register
V
DD
V
Ref
V
SS
PWDN
ESt
St/GT
Figure 1 - Functional Block Diagram
4-71
MT88L85
IN+
IN-
GS
VRef
VSS
OSC1
OSC2
NC
NC
TONE
R/W/WR
CS
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VDD
St/GT
ESt
D3
D2
D1
D0
NC
PWDN
IRQ/CP
DS/RD
RS0
GS
NC
IN-
IN+
VDD
St/GT
ESt
5
6
7
8
9
10
11
4
3
2
1
28
27
26
•
Advance Information
24 PIN DIP/SSOP
Figure 2 - Pin Connections
Pin Description
Pin #
24
1
2
3
4
5
6
7
10
11
12
13
14
15
28
1
2
4
6
7
8
9
12
14
15
17
18
Name
IN+
IN-
GS
V
Ref
V
SS
OSC1
OSC2
TONE
CS
RS0
Non-inverting
op-amp input.
Inverting
op-amp input.
Gain Select.
Gives access to output of front end differential amplifier for connection of
feedback resistor.
Reference Voltage
output (V
DD
/2).
Ground (0V).
Oscillator
input. This pin can also be driven directly by an external clock.
Oscillator
output. A 3.579545 MHz crystal connected between OSC1 and OSC2 completes
the internal oscillator circuit. Leave open circuit when OSC1 is driven externally.
Output from internal DTMF transmitter.
Chip Select
input. This signal must be qualified externally by either address strobe (AS),
valid memory address (VMA) or address latch enable (ALE) signal, see Figure 12.
Register Select
input. Refer to Table 3 for bit interpretation. CMOS compatible.
Description
13 R/W(WR) (Motorola)
Read/Write
or (Intel)
Write
microprocessor input. CMOS compatible.
DS
(RD)
(Motorola)
Data Strobe
or (Intel)
Read
microprocessor input. Activity on this input is only
required when the device is being accessed. CMOS compatible.
IRQ/CP
Interrupt Request/Call Progress
(open drain) output. In interrupt mode, this output goes
low when a valid DTMF tone burst has been transmitted or received. In call progress mode,
this pin will output a rectangular signal representative of the input signal applied at the input
op-amp. The input signal must be within the bandwidth limits of the call progress filter, see
Figure 8.
PWDN
Power Down
(input). Active High. Powers down the device and inhibits the oscillator. IRQ
and TONE output are high impedance. Data bus is held in tri-state. This pin is internally
pulled down.
Microprocessor data bus. High impedance when CS = 1 or DS =0 (Motorola) or RD = 1
(Intel). TTL compatible.
Early Steering
output. Presents a logic high once the digital algorithm has detected a valid
tone pair (signal condition). Any momentary loss of signal condition will cause ESt to return
to a logic low.
Steering Input/Guard Time
output (bidirectional). A voltage greater than V
TSt
detected at
St causes the device to register the detected tone pair and update the output latch. A
voltage less than V
TSt
frees the device to accept a new tone pair. The GT output acts to
reset the external steering time-constant; its state is a function of ESt and the voltage on St.
Positive power supply (3V typ.).
16
19
14- 18-
17 21
18
22
D0-D3
ESt
19
23
St/GT
20
4-72
24
V
DD
TONE
R/W/WR
CS
RS0
NC
DS/RD
IRQ/CP
12
13
14
15
16
17
18
NC
VRef
VSS
OSC1
OSC2
NC
NC
25
24
23
22
21
20
19
NC
D3
D2
D1
D0
NC
PWDN
28 PIN PLCC
Advance Information
Pin Description
Pin #
24
28
16,
20,
25
MT88L85
Name
NC
No Connection.
Description
8,9
3,5,
17
10,11
Functional Description
The MT88L85 Integrated DTMF Transceiver consists
of a high performance DTMF receiver with an
internal gain setting amplifier and a DTMF generator,
which employs a burst counter to synthesize precise
tone bursts and pauses. A call progress mode can
be selected so that frequencies within the specified
passband can be detected. The adaptive micro
interface allows microcontrollers, such as the
68HC11, 80C51 and TMS370C50, to access the
MT88L85 internal registers.
Receiver Section
Separation of the low and high group tones is
achieved by applying the DTMF signal to the inputs
of two sixth-order switched capacitor bandpass
filters, the bandwidths of which correspond to the low
and high group frequencies (see Table 1). The filters
also incorporate notches at 350 Hz and 440 Hz for
exceptional dial tone rejection. Each filter output is
followed by a single order switched capacitor filter
section, which smooths the signals prior to limiting.
Limiting is performed by high-gain comparators
which are provided with hysteresis to prevent
detection of unwanted low-level signals. The outputs
of the comparators provide full rail logic swings at
the frequencies of the incoming DTMF signals.
MT88L85
IN+
IN-
Power Down
The MT88L85 provides enhanced power down
functionality to facilitate minimization of supply
current consumption. DTMF transmitter and receiver
circuit blocks may be independently powered down
via register control. When asserted, the RxEN
control bit powers down all analog and digital
circuitry associated solely with the DTMF and Call
Progress receiver. The TOUT control bit is used to
disable the transmitter and put all circuitry
associated only with the DTMF transmitter in power
down mode. With the TOUT control bit asserted, the
TONE output pin is held in a high impedance
(floating) state. When both power down control bits
are asserted, circuits utilized by both the DTMF
transmitter and receiver are also powered down.
This includes the crystal oscillators, and the VRef
generator. In addition, the IRQ , TONE output and
DATA pins are held in a high impedance state.
Finally, the whole device is put in a power down state
when the PWDN pin is asserted.
C
R
IN
R
F
VOLTAGE GAIN
(A
V
) = R
F
/ R
IN
GS
V
Ref
Figure 3 - Single-Ended Input Configuration
MT88L85
C1
R1
IN+
IN-
C2
R4
R5
GS
Input Configuration
R3
R2
V
Ref
DIFFERENTIAL INPUT AMPLIFIER
C1 = C2 = 10 nF
R1 = R4 = R5 = 100 kΩ
R2 = 60kΩ, R3 = 37.5 kΩ
R3 = (R2R5)/(R2 + R5)
VOLTAGE GAIN
INPUT IMPEDANCE
(A
V
diff) - R5/R1
(Z diff) = 2 R1
2
+ (1/ωC)
2
IN
The input arrangement of the MT88L85 provides a
differential-input operational amplifier as well as a
bias source (V
Ref
), which is used to bias the inputs at
V
DD
/2. Provision is made for connection of a
feedback resistor to the op-amp output (GS) for gain
adjustment. In a single-ended configuration, the
input pins are connected as shown in Figure 3.
Figure 4 shows the necessary connections for a
differential input configuration.
Figure 4 - Differential Input Configuration
4-73
MT88L85
F
LOW
F
HIGH
DIGIT
D
3
D
2
D
1
D
0
Advance Information
(V
TSt
) of the steering logic to register the tone pair,
latching its corresponding 4-bit code (see Table 1)
into the Receive Data Register. At this point the GT
output is activated and drives v
c
to V
DD
. GT
continues to drive high as long as ESt remains high.
Finally, after a short delay to allow the output latch to
settle, the delayed steering output flag goes high,
signalling that a received tone pair has been
registered. The status of the delayed steering flag
can be monitored by checking the appropriate bit in
the status register. If Interrupt mode has been
selected, the IRQ/CP pin will pull low when the
delayed steering flag is active.
The contents of the output latch are updated on an
active delayed steering transition. This data is
presented to the four bit bidirectional data bus when
the Receive Data Register is read. The steering
circuit works in reverse to validate the interdigit
pause between signals. Thus, as well as rejecting
signals too short to be considered valid, the receiver
will tolerate signal interruptions (drop out) too short
to be considered a valid pause. This facility, together
with the capability of selecting the steering time
constants externally, allows the designer to tailor
performance to meet a wide variety of system
requirements.
V
DD
697
697
697
770
770
770
852
852
852
941
941
941
697
770
852
941
1209
1336
1477
1209
1336
1477
1209
1336
1477
1336
1209
1477
1633
1633
1633
1633
1
2
3
4
5
6
7
8
9
0
*
#
A
B
C
D
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0= LOGIC LOW, 1= LOGIC HIGH
Table 1. Functional Encode/Decode Table
Following the filter section is a decoder employing
digital counting techniques to determine the
frequencies of the incoming tones and to verify that
they correspond to standard DTMF frequencies. A
complex averaging algorithm protects against tone
simulation by extraneous signals such as voice while
providing tolerance to small frequency deviations
and variations. This averaging algorithm has been
developed to ensure an optimum combination of
immunity to talk-off and tolerance to the presence of
interfering frequencies (third tones) and noise. When
the detector recognizes the presence of two valid
tones (this is referred to as the “signal condition” in
some industry specifications) the “Early Steering”
(ESt) output will go to an active state. Any
subsequent loss of signal condition will cause ESt to
assume an inactive state.
MT88L85
V
DD
St/GT
ESt
R1
C1
Vc
t
GTA
= (R1C1) In (V
DD
/ V
TSt
)
t
GTP
= (R1C1) In [V
DD
/ (V
DD
-V
TSt
)]
Figure 5 - Basic Steering Circuit
Guard Time Adjustment
The simple steering circuit shown in Figure 5 is
adequate for most applications. Component values
are chosen according to the following inequalities
(see Figure 7):
t
REC
≥
t
DPmax
+ t
GTPmax
- t
DAmin
t
REC
≤
t
DPmin
+ t
GTPmin
- t
DAmax
t
ID
≥
t
DAmax
+ t
GTAmax
- t
DPmin
t
DO
≤
t
DAmin
+ t
GTAmin
- t
DPmax
The value of t
DP
is a device parameter (see AC
Electrical Characteristics) and t
REC
is the minimum
Steering Circuit
Before registration of a decoded tone pair, the
receiver checks for a valid signal duration (referred
to as character recognition condition). This check is
performed by an external RC time constant driven by
ESt. A logic high on ESt causes v
c
(see Figure 5) to
rise as the capacitor discharges. Provided that the
signal condition is maintained (ESt remains high) for
the validation period (t
GTP
), v
c
reaches the threshold
4-74
Advance Information
signal duration to be recognized by the receiver. A
value for C1 of 0.1 µF is recommended for most
MT88L85
applications, leaving R1 to be selected by the
designer. Different steering arrangements may be
used to select independent tone present (t
GTP
) and
tone absent (t
GTA
) guard times. This may be
necessary to meet system specifications which place
both accept and reject limits on tone duration and
interdigital pause. Guard time adjustment also allows
the designer to tailor system parameters such as talk
off and noise immunity.
Increasing t
REC
improves talk-off performance since
it reduces the probability that tones simulated by
speech will maintain a valid signal condition long
enough to be registered. Alternatively, a relatively
short t
REC
with a long t
DO
would be appropriate for
extremely noisy environments where fast acquisition
time and immunity to tone drop-outs are required.
Design information for guard time adjustment is
shown in Figure 6. The receiver timing is shown in
Figure 7 with a description of the events in Figure 9.
t
GTP
= (R
P
C1) In [V
DD
/ (V
DD
-V
TSt
)]
t
GTA
= (R1C1) In (V
DD
/V
TSt
)
V
DD
C1
St/GT
R
P
= (R1R2) / (R1 + R2)
R1
ESt
R2
a) decreasing tGTP; (tGTP < tGTA)
t
GTP
= (R1C1) In [V
DD
/ (V
DD
-V
TSt
)]
V
DD
C1
St/GT
t
GTA
= (R
p
C1) In (V
DD
/V
TSt
)
R
P
= (R1R2) / (R1 + R2)
Call Progress Filter
R1
R2
b) decreasing tGTA; (tGTP > tGTA)
ESt
Figure 6 - Guard Time Adjustment
A call progress mode, using the MT88L85, can be
selected allowing the detection of various tones,
which identify the progress of a telephone call on the
network. The call progress tone input and DTMF
input are common, however, call progress tones can
only be detected when CP mode has been selected.
C
D
E
F
EVENTS
A
B
t
REC
V
in
t
REC
TONE #n
t
ID
TONE
#n + 1
t
DO
TONE
#n + 1
t
DP
ESt
t
DA
t
GTP
t
GTA
V
TSt
St/GT
t
PStRX
RX
0
-RX
3
DECODED TONE # (n-1)
#n
# (n + 1)
t
PStb3
b3
b2
Read
Status
Register
IRQ/CP
Figure 7 - Receiver Timing Diagram
4-75
PCB设计
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