DATA SHEET
256MB, 512MB Registered DDR SDRAM DIMM
HB54A2569F1 (32M words
×
72 bits, 1 Bank)
HB54A5129F2 (64M words
×
72 bits, 2 Banks)
Description
The HB54A2569F1, HB54A5129F2 are Double Data
Rate (DDR) SDRAM Module, mounted 256M bits DDR
SDRAM (HM5425801BTT) sealed in TSOP package, 1
piece of PLL clock driver, 2 pieces of register driver
and 1 piece of serial EEPROM (2k bits EEPROM) for
Presence Detect (PD).
The HB54A2569F1 is organized as 32M
×
72
×
1 bank
mounted 9 pieces of 256M bits DDR SDRAM. The
HB54A5129F2 is organized as 32M
×
72
×
2 banks
mounted 18 pieces of 256M bits DDR SDRAM. Read
and write operations are performed at the cross points
of the CK and the /CK. This high-speed data transfer
is realized by the 2 bits prefetch-pipelined architecture.
Data strobe (DQS) both for read and write are available
for high speed and reliable data bus design. By setting
extended mode register, the on-chip Delay Locked
Loop (DLL) can be set enable or disable. An outline of
the products is 184-pin socket type package (dual lead
out).
Therefore, it makes high density mounting
possible without surface mount technology. It provides
common data inputs and outputs.
Decoupling
capacitors are mounted beside each TSOP on the
module board.
Features
•
184-pin socket type package (dual lead out)
Outline: 133.35mm (Length)
×
43.18mm (Height)
×
4.00mm (Thickness)
Lead pitch: 1.27mm
•
2.5V power supply (VCC/VCCQ)
•
SSTL-2 interface for all inputs and outputs
•
Clock frequency: 143MHz/133MHz/125MHz (max.)
•
Data inputs, outputs and DM are synchronized with
DQS
•
4 banks can operate simultaneously and
independently (Component)
•
Burst read/write operation
•
Programmable burst length: 2, 4, 8
Burst read stop capability
•
Programmable burst sequence
Sequential
Interleave
•
Start addressing capability
Even and Odd
•
Programmable /CAS latency (CL): 3, 3.5
•
8192 refresh cycles: 7.8µs (8192/64ms)
•
2 variations of refresh
Auto refresh
Self refresh
EO
Document No. E0091H40 (Ver. 4.0)
Date Published September 2002 (K) Japan
URL: http://www.elpida.com
L
This product became EOL in May, 2004.
Elpida
Memory, Inc. 2001-2002
Hitachi,
Ltd. 2001
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
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HB54A2569F1, HB54A5129F2
Pin Description
Pin name
A0 to A12
BA0, BA1
DQ0 to DQ63
CB0 to CB7
/RAS
/CAS
/WE
/S0, /S1
Function
Address input
Row address
Column address
Data input/output
Check bit (Data input/output)
Row address strobe command
Column address strobe command
Write enable
Chip select
Clock enable
Clock input
Differential clock input
Input and output data strobe
Input mask
Clock input for serial PD
Data input/output for serial PD
Serial address input
Power for internal circuit
Power for DQ circuit
Power for serial EEPROM
Input reference voltage
A0 to A12
A0 to A9
Bank select address
EO
CKE0, CKE1
CK0
/CK0
DQS0 to DQS8
SCL
SDA
SA0 to SA2
VCC
VCCQ
VCCSPD
VREF
VSS
VCCID
/RESET
NC
DM0 to DM8/DQS9 to DQS17
Data Sheet E0091H40 (Ver. 4.0)
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Ground
VCC identification flag
Reset pin (forces register inputs low)
No connection
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4
HB54A2569F1, HB54A5129F2
Serial PD Matrix*
Byte No.
0
1
2
3
4
5
1
Function described
Number of bytes utilized by module
manufacturer
Total number of bytes in serial PD
device
Memory type
Number of row address
Number of column address
Number of DIMM banks
HB54A2569F1
HB54A5129F2
Module data width
Module data width continuation
Bit7
1
0
0
0
0
0
0
0
0
Bit6
0
0
0
0
0
0
0
1
0
0
1
1
0
1
0
0
0
0
0
Bit5 Bit4
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
Bit3
0
1
0
1
1
0
0
1
0
0
0
0
0
0
0
0
0
1
1
Bit2
0
0
1
1
0
0
0
0
0
1
0
1
0
1
0
0
0
0
0
Bit1 Bit0
0
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
Hex value
80H
08H
07H
0DH
0AH
01H
02H
48H
00H
04H
70H
75H
80H
75H
80H
02H
82H
08H
08H
Comments
128
256 bytes
SDRAM DDR
13
10
1
2
72 bits
0 (+)
SSTL 2.5V
CL = 2.5*
5
6
7
8
9
EO
-B75B
-10B
10
-10B
11
12
13
14
15
16
17
18
19
20
21
22
23
-B75B/10B
24
-10B
25
26
Voltage interface level of this assembly 0
0
0
1
0
1
0
1
0
0
DDR SDRAM cycle time, CL = X
-A75B
SDRAM access from clock (tAC)
-A75B, -B75B
0.75ns*
5
0.8ns*
5
ECC
7.8 µs
Self refresh
×
8
×
8
1 CLK
2, 4, 8
4
2, 2.5
0
1
Registered
± 0.2V
CL = 2*
5
DIMM configuration type
Refresh rate/type
Primary SDRAM width
Error checking SDRAM width
SDRAM device attributes:
Minimum clock delay back-to-back
column access
SDRAM device attributes:
Burst length supported
SDRAM device attributes: Number of
banks on SDRAM device
SDRAM device attributes:
/CAS latency
SDRAM device attributes:
/CS latency
SDRAM device attributes:
/WE latency
SDRAM module attributes
SDRAM device attributes: General
Minimum clock cycle time at
CLX - 0.5
-A75B
Maximum data access time (tAC) from
clock at CLX - 0.5
0
-A75B, -B75B
1
Minimum clock cycle time at
0
CLX - 1
Maximum data access time (tAC) from
0
clock at CLX - 1
Data Sheet E0091H40 (Ver. 4.0)
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0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
1
1
0
0
0
0
0
1
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
1
1
0
1
1
0
0
0
0
0
0
0
1
1
0
1
0
0
0
1
1
1
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
01H
0EH
04H
0CH
01H
02H
26H
C0H
75H
t
uc
A0H
75H
0.75ns*
5
0.8ns*
5
80H
00H
00H
5
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