MT90863
3V Rate Conversion Digital Switch
Advance Information
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
2,048
×
512 and 512 x 512 switching among
backplane and local streams
Rate conversion between 2.048, 4.096 and
8.192Mb/s
Optioal sub-rate switch configuration for
2.048 Mb/s streams
Per-channel variable or constant throughput
delay
Compatible to HMVIP and H.100 specifications
Automatic frame offset delay measurement
Per-stream frame delay offset programming
Per-channel message mode
Per-channel direction control
Per-channel high impedance output control
Non-multiplexed microprocessor interface
Connection memory block programming
3.3V local I/O with 5V tolerant inputs and
TTL-compatible outputs
IEEE-1149.1 (JTAG) Test Port
DS5034
ISSUE 3
March 1999
Ordering Information
MT90863AL1
MT90863AG1
128 Pin MQFP
144 Pin BGA
-40 to +85 C
Description
The MT90863 Rate Conversion Switch provides
switching capacities of 2,048
×
512 channels
between backplane and local streams, and 512 x
512 channels for local streams. The connected serial
inputs and outputs may have 32, 64 and 128 64kb/s
channels per frame with data rates of 2.048Mb/s,
4.096Mb/s and 8.192Mb/s respectively.
The MT90863 also offers a sub-rate switching
configuration which allows 2-bit wide 16kb/s data
channels to be switched within the device.
The device has features (such as: message mode;
input and output offset delay; direction control; and,
high
impedance
output
control)
that
are
programmable on per-stream or per-channel basis.
Applications
•
•
•
•
Medium and large switching platforms
CTI application
Voice/data multiplexer
Support ST-BUS, HMVIP and H.100 interfaces
ODE
STio0/
FEi0
STio15/
FEi15
STio16/
FEi16
STio23/
FEi23
STio24
STio31
C16i
F0i
C4i/C8i
Backplane
Interface
S/P
&
P/S
Converter
V
DD
V
SS
ODE
STo0
Multiple Buffer
Data Memory
(2,048 channels)
Local
Connection
Memory High/Low
(512 locations)
Output
Mux
Local
Interface
P/S
Converter
Multiple Buffer
Data Memory
(512 channels)
Local
Interface
Multiple Buffer
Data Memory
(512 channels)
S/P
Converter
STo11
STo12
STo13
STo15
STi0
STi11
STi12
STi13
STi15
RESET
IC1
IC2
Internal
Registers
Timing
Unit
Backplane
Connection
Memory
(2,048 locations)
Microprocessor Interface
Test Port
F0o C4o
DS CS R/W
A7-A0
DTA D15-D0
TMS TDI TDO TCK TRST
Figure 1 - Functional Block Diagram
1
MT90863
Advance Information
VSS
C4o
F0o
VSS
C4i/C8i
F0i
VSS
C16i
VSS
ST015
STo14
STo13
STo12
STo11
STo10
STo9
STo8
VDD
VSS
STo7
STo6
STo5
STo4
STo3
STo2
STo1
STo0
ODE
VSS
VDD
STi15
STi14
95
93
91
89
87
85
83
81
79
77
75
73
71
69
67
65
63
99
61
101
59
103
57
105
55
107
53
109
51
111
113
47
115
45
117
43
119
41
121
39
123
37
125
35
127
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
VDD
STio0/FEi0
STio1/FEi1
STio2/FEi2
STio3/FEi3
STio4/FEi4
STio5/FEi5
STio6/FEi6
STio7/FEi7
VSS
VDD
STio8/FEi8
STio9/FEi9
STio10/FEi10
STio11/FEi11
STio12/FEi12
STio13/FEi13
STio14/FEi14
STio15/FEi15
VSS
VDD
STio16/FEi16
STio17/FEi17
STio18/FEi18
STio19/FEi19
STio20/FEi20
STio21/FEi21
STio22/FEi22
STio23/FEi23
VSS
VDD
STio24
97
128 Pin PQFP
49
STi13
STi12
STi11
STi10
STi9
STi8
STi7
STi6
STi5
STi4
STi3
STi2
STi1
STi0
VDD
VSS
DTA
D15
D14
D13
D12
D11
D10
D9
D8
VSS
D7
D6
D5
D4
D3
D2
2
STio25
STio26
STio27
STio28
STio29
STio30
STio31
VSS
TMS
TDI
TDO
TCK
TRST
IC1
RESET
IC2
VSS
A0
A1
A2
A3
A4
A5
A6
A7
DS
R/W
CS
VSS
VDD
D0
D1
Figure 2 - MQFP Pin Connections
Advance Information
MT90863
1
2
3
4
5
6
7
8
9
10
11
12
13
1
A
STio26 STio24 STio22 STio19 STio17 STio15 STio14 STio11 STio8 STio6 STio4 STio3
B
F0o
STio29 STio25 STio23 STio20 STio18 STio16 STio13 STio10 STio7 STio5 STio2 STio1 C4i/C8i
C
TMS STio28 STio27 STio21 VDD
D
TDI STio31 STio30 VSS
E
TCK
F
RESET TRST
G
A0
H
A1
J
A5
K
A7
L
CS
M
D0
N
D1
D3
D6
D9
D13
D14
DTA
STi0
STi2
STi3
STi5
STi9 STi11
D2
D4
D8
D10
D12
D15
STi1
STi4
STi7 STi10 STi13 STi14
R/W
VSS
D5
D7
D11
VSS
VDD
STi6
STi8 STi12 STi15 ODE
DS
VDD
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VDD
STo1 STo0
A4
A6
VSS
VSS
VSS
STo3 STo2
A2
A3
VDD
VSS
STo4
STo6 STo5
VSS
IC2
VSS
IC1
VDD
VSS
VSS
VDD
STo10 STo9
STo8 STo7
TDO
VSS
VSS
VDD STo14 STo12 STo11
VDD
VSS
VDD
VSS
VDD
VSS
F0i
C16i STo13
VSS STio12 STio9 VDD
VSS STio0
C4o STo15
TOP VIEW
VDD
1
- A1 corner is identified by metallized markings.
Figure 3 - BGA Pin Connections
Pin Description
128 MQFP
Pin#
144 BGA
Pin#
Name
V
DD
+3.3 Volt Power Supply
Description
30,50,67, C5,C9,D5,D7,
79,97,107, D9,E10,F4,G10
117,127
,G11,H4,
K3,K4,K6,K8
K10,K11,L8
8,17,29,39, C6,C10,D4,D6,
49,68,78,8 D8,D10,E3,E4,
8,90,93,96, F10,F11,G2,
106,
G4,H10,J4,
116,126
J10,J11,K5
K7,K9,L3,L7
89
91
D12
D11
V
ss
Ground
C16i
F0i
Master Clock (5V Tolerant Input):
Serial clock for shifting data in/out
on the serial streams. This pin accepts a 16.384 MHz clock.
Master Frame Pulse (5V Tolerant Input):
In ST-BUS mode, this input
accepts a 61ns wide negative frame pulse. In CT Bus mode, it accepts
a 122ns wide negative frame pulse. In HMVIP mode, it accepts a
244ns wide negative frame pulse.
3
MT90863
Pin Description (continued)
128 MQFP
Pin#
92
144 BGA
Pin#
B13
Name
C4i/C8i
Description
Advance Information
HMVIP/CT Bus Clock (5V Tolerant Input):
When HMVIP mode is
enabled, this pin accepts a 4.096MHz clock for HMVIP frame pulse
alignment. When CT Bus mode is enabled, it accepts a 8.192MHz
clock for CT frame pulse alignment.
Frame Pulse (5V Tolerant Output):
A 244ns wide negative frame
pulse that is phase locked to the master frame pulse (F0i).
C4 Clock (5V Tolerant Output):
A 4.096MHz clock that is phase
locked to the master clock (C16i).
94
95
98-105,
108-115
A13
C12
C11, B12, B11,
A12, A11, B10,
A10, B9, A9,
C8, B8, A8, C7,
B7, A7, A6,
F0o
C4o
STio0 - 15
Serial Input Streams 0 to 15 / Frame Evaluation Inputs 0 to 15 (5V
FEi0 - 15
Tolerant I/O).
In 2Mb/s and HMVIP modes, these pins accept serial
TDM data streams at 2.048 Mb/s with 32 channels per stream. In 4Mb/
s or 8Mb/s mode, these pins accept serial TDM data streams at 4.096
or 8.192 Mb/s with 64 or 128 channels per stream respectively. In
Frame Evaluation Mode (FEM), they are frame evaluation inputs.
118-125
B6, A5, B5, A4, STio16 - 23
Serial Input Streams 16 to 23 (5V Tolerant I/O).
In 2Mb/s or 4Mb/s
B4, C4, A3, B3 FEi16 - 23 mode, these pins accept serial TDM data streams at 2.048 or 4.096
Mb/s with 32 or 64 channels per stream respectively. In HMVIP mode,
these pins have a data rate of 8.192Mb/s with 128 channels per
stream. In Frame Evaluation Mode (FEM), they are frame evaluation
inputs.
A2, B2, A1, C3, STio24 - 31
Serial Input Streams 24 to 31 (5V Tolerant I/O).
These pins are only
C2, B1, D3, D2
used for 2Mb/s or 4Mb/s mode. They accept serial TDM data streams
at 2.048 or 4.096 Mb/s with 32 or 64 channels per stream respectively.
C1
D1
E2
TMS
TDI
TDO
Test Mode Select (3.3V Input with internal pull-up):
JTAG signal
that controls the state transitions of the TAP controller.
Test Serial Data In (3.3V Input with internal pull-up):
JTAG serial
test instructions and data are shifted in on this pin.
Test Serial Data Out (3.3V Output):
JTAG serial data is output on this
pin on the falling edge of TCK. This pin is held in a high impedance
state when JTAG scan is not enabled.
Test Clock (5V Tolerant Input):
Provides the clock to the JTAG test
logic.
Test Reset (3.3 V Input with internal pull-up):
Asynchronously
initializes the JTAG TAP controller by putting it in the Test-Logic-Reset
state. This pin should be pulsed low on power-up, or held low
continuously, to ensure that the MT90863 is in the normal operation
mode.
Internal Connection 1 (3.3V Input with internal pull-down):
Connect to V
SS
for normal operation.
Device Reset (5V Tolerant Input):
This input (active LOW) puts the
MT90863 in its reset state. This clears the device’s internal counters
and registers. It also brings microport data bus STio0 - 31 and STo0 -
15 to a high impedance state.
Internal Connection 2 (3.3V Input):
Connect to V
SS
for normal operation.
128,
1-7
9
10
11
12
13
E1
F2
TCK
TRST
14
15
F3
F1
IC1
RESET
16
G3
IC2
4
Advance Information
Pin Description (continued)
128 MQFP
Pin#
18-25
144 BGA
Pin#
G1, H1, H2,
H3, J2, J1,J3,
K1
K2
L2
L1
M1, N1, M2, N2,
M3, L4, N3, L5,
M4, N4, M5,
L6, M6, N5, N6,
M7,
N7
Name
A0 - A7
Description
MT90863
Address 0 - 7 (5V Tolerant Input):
These lines provide the A0 to A7
address lines to the internal memories.
Data Strobe (5V Tolerant Input):
This active low input works in
conjunction with CS to enable the read and write operations.
Read/Write (5V Tolerant Input):
This input controls the direction of
the data bus lines (D0-D15) during a microprocessor access.
Chip Select (5V Tolerant Input):
Active low input used by a
microprocessor to activate the microprocessor port.
Data Bus 0 -15 (5V Tolerant I/O):
These pins form the 16-bit data bus
of the microprocessor port.
26
27
28
31-38,
40-47
DS
R/W
CS
D0 - 7,
D8 - D15
48
DTA
Data Transfer Acknowledgment (5V Tolerant Three-state Output):
This active low output indicates that a data bus transfer is complete. A
pull-up resistor is required to hold a HIGH level when the pin is tri-
stated.
Serial Input Streams 0 to 3 (5V Tolerant Inputs):
In 2Mb/s or
Subrate Switching mode, these inputs accept data rates of 2.048 Mb/s
with 32 channels per stream. In 8Mb/s mode, these inputs accept data
rates of 8.192 Mb/s with 128 channels per stream.
Serial Input Streams 4 to 11 (5V Tolerant Inputs):
In 2Mb/s or Sub-
rate Switching mode, these inputs accept data rates of 2.048Mb/s
with 32 channels per stream.
Serial Input Streams 12 (5V Tolerant Input):
In 2Mb/s mode, this
input accepts data rate of 2.048Mb/s with 32 channels per stream
respectively. In Sub-rate Switching mode, this pin accepts 2.048Mb/s
with 128 channels per stream for Sub-rate switching application.
51-54
N8, M8, N9,
N10
STi0 - 3
55-62
M9, N11, L9,
M10, L10, N12,
M11, N13
L11
STi4 - 11
63
STi12
64-66
M12, M13, L12
STi13 - 15
Serial Input Streams 13 to 15 (5V Tolerant Inputs):
In 2Mb/s mode,
these inputs accept a data rate of 2.048Mb/s with 32 channels per
stream.
ODE
Output Drive Enable (5V Tolerant Input):
This is the output enable
control for the STo0 to STo15 serial outputs and STio0 to STio31 serial
bidirectional outputs.
Serial Output Streams 0 to 3 (5V Tolerant Three-state Outputs):
In
2Mb/s or Sub-rate Switching mode, these outputs have data rates of
2.048 Mb/s with 32 channels per stream respectively. In 8Mb/s mode,
these outputs have data rates of 8.192 Mb/s with 128 channels per
stream
69
L13
70-73
K13, K12, J13,
J12
STo0 - 3
74-77,
80-83
H11, H13, H12,
G13, G12, F13,
F12, E13
STo4 - 7,
Serial Output Streams 4 to 11 (5V Tolerant Three-state Outputs):
STo8 - 11 In 2Mb/s or Sub-rate Switching mode, these outputs have data rates of
2.048Mb/s with 32 channels per stream
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
