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MT90221: 产品描述quad ima/uni phy device; 文件大小306KB，共114页; 制造商Mitel; 官网地址https://www.mitel.com

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MT90221概述

quad ima/uni phy device

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MT90221

Quad IMA/UNI PHY Device

Features

•

Cost effective, single chip, 4-port ATM IMA and

UNI processor

Up to 4 IMA groups over 4 T1/E1 links can be

implemented

Supports MIXED mode; links not assigned to an

IMA group can be used in UNI mode

Versatile PCM Interface to most popular T1 or

E1 framers, reducing development time

Supports Symmetrical and Asymmetrical

Operation

Supports both Common Transmit Clock (CTC)

and Independent Transmit Clock (ITC) clocking

modes

Supports T1 ISDN lines

Provides UTOPIA Level 2 MPHY Interface

(MT90221 device slaved to ATM device)

Complies with ITU G.804 recommendations for

performing cell mapping into T1 and E1

transmission systems

Provides ATM framing using cell delineation

according to the ITU I.432 cell delineation

process

DS5065

ISSUE 4

December 1999

Ordering Information

MT90221AL

208 Pin MQFP

-40°C to +85°C

•

Provides Header Error Control (HEC)

veriﬁcation and generation, error detection,

Filler cell ﬁltering (IMA mode) and Idle/

Unassigned cell ﬁltering (UNI mode)

Provides statistics to support MIB

Connects to popular asychronous SRAM

Provides statistics on the number of HEC errors

8 bit Microprocessor Interface, compatible with

Intel and Motorola

3.3V operation / 5V tolerant inputs

MQFP-208 pin

JTAG Test support

•

RX External Static RAM

4 Internal

IMA

Processors

T1/E1

Framers

2.048 or

1.544 Mb/s

Utopia

I/F CTRL

Utopia

Level 2

BUS

P/S

Cell

Delineator

4 x CD Circuit

P/S

T1/E1

Framers

Utopia FiFo

Transmission

4 x TC Circuit

Convergence 1

T1/E1

Framers

4 Serial PCM Ports

Processor I/F

Figure 1 - MT90221 Block Diagram with Built-in IMA functions for 4 IMA Groups over up to 4 links

MT90221

Table of Contents

1.0 Device Architecture .......................................................................................................................................

1.1 Software Functions.....................................................................................................................................

1.1.1 Link State Machines...........................................................................................................................

1.1.2 IMA Group State Machines ................................................................................................................

1.1.3 Link Addition, Removal or Restoration...............................................................................................

1.1.4 Interrupt..............................................................................................................................................

1.1.5 Signaling and Rate Adjustment..........................................................................................................

1.1.6 Performance Monitoring.....................................................................................................................

1.2 Hardware Functions ...................................................................................................................................

2.0 The ATM Transmit Path ................................................................................................................................. 9

2.1 Cell_In_Control........................................................................................................................................... 9

2.2 The ATM Transmission Convergence ...................................................................................................... 10

2.2.1 TX Cell Ram and TX FIFO Length ................................................................................................... 10

2.3 Parallel to Serial PCM Interface ............................................................................................................... 11

2.4 ATM Transmit Path in IMA Mode ............................................................................................................. 11

2.4.1 IMA Frame Length (M) ..................................................................................................................... 11

2.4.2 Position of the ICP Cell in the IMA Frame........................................................................................ 11

2.4.3 Transmit Clock Operation ................................................................................................................ 11

2.4.4 Stuff Cell Rate .................................................................................................................................. 12

2.4.5 IMA Data Cell Rate .......................................................................................................................... 12

2.4.6 IMA Controller (RoundRobin Scheduler).......................................................................................... 12

2.4.7 ICP Cell Generator........................................................................................................................... 12

2.4.8 IMA Frame Programmable Interrupt ................................................................................................ 14

2.4.9 Filler Cell Definition .......................................................................................................................... 14

2.4.10 TX IMA Group Start-Up.................................................................................................................... 14

2.4.11 TX Link Addition ............................................................................................................................... 14

2.4.12 TX Link Deletion............................................................................................................................... 14

2.5 ATM Transmit Path in UNI Mode ............................................................................................................. 14

3.0 The ATM Receive Path................................................................................................................................. 15

3.1 Cell Delineation Function ......................................................................................................................... 15

3.2 De-Scrambling and ATM Cell Filtering ..................................................................................................... 16

3.3 ATM Receive Path in IMA Mode .............................................................................................................. 16

3.3.1 ICP Cell Processor........................................................................................................................... 17

3.3.1.1 IMA Frame Synchronization...................................................................................................... 17

3.3.1.2 Link Information......................................................................................................................... 18

3.3.1.3 RX OAM Label .......................................................................................................................... 18

3.3.2 Out of IMA Frame (OIF) Condition ................................................................................................... 18

3.3.3 Link Out Of IMA Frame (LIF) Synchronization ................................................................................. 18

3.3.4 Filler Cell Handling ........................................................................................................................... 18

3.3.5 Stuff Cell Handling ........................................................................................................................... 18

3.3.6 Received ICP Cell Buffer .................................................................................................................. 18

MT90221

Table of Contents

3.3.7 Rate Recovery ................................................................................................................................. 19

3.3.8 Cell Buffer/RAM Controller............................................................................................................... 19

3.3.9 Cell Sequence Recovery ................................................................................................................. 19

3.3.10 Delay Between Links ....................................................................................................................... 20

3.3.10.1 RX Recombiner Delay Value .................................................................................................... 20

3.3.10.2 RX Maximum Operational Delay Value..................................................................................... 20

3.3.10.3 Link Out of Delay Synchronization (LODS)............................................................................... 20

3.3.10.4 Negative Delay Values.............................................................................................................. 21

3.3.10.5 Measured Delay Between Links................................................................................................ 21

3.3.10.6 Incrementing/Decrementing the Recombiner Delay ................................................................. 21

3.3.11 RX IMA Group Start-Up ................................................................................................................... 22

3.3.12 Link Addition .................................................................................................................................... 22

3.3.13 Link Deletion .................................................................................................................................... 22

3.3.14 Disabling an IMA Group ................................................................................................................... 22

3.4 The ATM Receive Path in UNI ................................................................................................................. 22

4.0 Description of the PCM Interface................................................................................................................

4.1 Serial to Parallel (S/P) and Parallel to Serial (P/S) Converters ................................................................

4.2 PCM System Interface Modes..................................................................................................................

4.2.1 Mode 2 and 6: ST-BUS Interface for T1 ..........................................................................................

4.2.1.1 Detailed ST-BUS Spaced Mapping (3 of Every 4 Channels) ....................................................

4.2.1.2 Detailed ST-BUS Grouped Mapping (24 Consecutive Channels).............................................

4.2.1.3 Detailed ST-BUS ISDN Mapping (T1 ISDN Modes) .................................................................

4.2.2 Mode 4 and 8: ST-BUS lnterface for E1 ..........................................................................................

4.2.3 Mode 1 and 5: Generic PCM Interface for T1 ..................................................................................

4.2.3.1 1.544 MHz Clock.......................................................................................................................

4.2.3.2 2.048 MHz Clock.......................................................................................................................

4.2.4 Mode 3 and 7: Generic PCM Interface for E1 ..................................................................................

4.2.5 TXSYNC Signal in Mode 5 and 7.....................................................................................................

4.3 Clocking Options ......................................................................................................................................

4.3.1 Verification of the RXSYNC Period ..................................................................................................

4.3.2 Verification of the TXSYNC Period ..................................................................................................

4.3.3 Primary and Secondary Reference Signals .....................................................................................

4.3.4 Verification of Clock Activity .............................................................................................................

4.3.5 Clock Selection ................................................................................................................................

5.0 UTOPIA Interface Operation........................................................................................................................

5.1 ATM Input Port .........................................................................................................................................

5.2 ATM Output Port ......................................................................................................................................

5.3 UTOPIA Operation With a Single PHY.....................................................................................................

5.4 UTOPIA Operation with Multiple PHY ......................................................................................................

5.5 UTOPIA Operation in UNI Mode ..............................................................................................................

5.6 UTOPIA Operation in IMA Mode ..............................................................................................................

5.7 Examples of UTOPIA Operation Modes...................................................................................................

MT90221

Table of Contents

6.0 Support Blocks.............................................................................................................................................

6.1 Counter Block...........................................................................................................................................

6.1.1 UTOPIA Input I/F counters...............................................................................................................

6.1.2 Transmit PCM I/F Counters .............................................................................................................

6.1.3 Receive PCM I/F Counters ..............................................................................................................

6.1.4 Access to the Counters ....................................................................................................................

6.2 Interrupt Block ..........................................................................................................................................

6.2.1 IRQ Master Status and IRQ Master Enable Registers.....................................................................

6.2.2 IRQ Link Status and IRQ Link Enable Registers..............................................................................

6.2.2.1 Bit 7 and 6 of IRQ Link 0 Status and IRQ Link 0 Enable Registers ..........................................

6.2.3 IRQ Link UNI Overflow and IRQ UTOPIA Input UNI Overflow Status Registers .............................

6.2.4 IRQ IMA Group Overflow Status and Enable Registers...................................................................

6.2.5 IRQ IMA Overflow Status and RX UTOPIA IMA Group FIFO Overflow Enable Registers ..............

6.3 Register and Memory Map .......................................................................................................................

6.3.1 Access to the Various Registers ......................................................................................................

6.3.2 Direct Access ...................................................................................................................................

6.3.3 Indirect Access.................................................................................................................................

6.3.4 Clearing of Status Bits......................................................................................................................

6.3.4.1 Toggle Bit ..................................................................................................................................

6.3.5 Test Modes ......................................................................................................................................

7.0 Register Descriptions ..................................................................................................................................

7.1 Utopia Register Description......................................................................................................................

7.2 TX Registers Description..........................................................................................................................

7.3 TX ICP Register Description ....................................................................................................................

7.4 RX Registers Description .........................................................................................................................

7.5 RX ICP Cell Registers Description ...........................................................................................................

7.6 External SRAM Register Description .......................................................................................................

7.7 RX Delay Registers Description ...............................................................................................................

7.8 RX Recombiner Registers Description .....................................................................................................

7.9 TX/RX and PLL Control Registers Description.........................................................................................

7.10 Counter Registers Description ................................................................................................................

7.11Interrupt Registers Description .................................................................................................................

7.12 Miscellaneous Registers Description ......................................................................................................

8.0 Application Notes......................................................................................................................................... 77

8.1 Connecting the MT90220 to Various T1/E1 Framers ............................................................................... 77

9.0 AC/DC Characteristics................................................................................................................................. 83

iii

MT90221相似产品对比

	MT90221	MT90221AL
描述	quad ima/uni phy device	quad ima/uni phy device

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