®
ISO-CMOS
MT8808
8 x 8 Analog Switch Array
Features
•
•
•
•
•
•
•
•
•
•
Internal control latches and address decoder
Short set-up and hold times
Wide operating voltage: 4.5V to 13.2V
12Vpp analog signal capability
R
ON
65Ω max. @ V
DD
=12V, 25°C
∆R
ON
≤
10Ω @ V
DD
=12V, 25°C
Full CMOS switch for low distortion
Minimum feedthrough and crosstalk
Separate analog and digital reference supplies
Low power consumption ISO-CMOS technology
ISSUE 2
November 1988
Ordering Information
MT8808AC
28 Pin Ceramic DIP
MT8808AE
28 Pin Plastic DIP
MT8808AP
28 Pin PLCC
-40° to 85°C
Description
The Mitel MT8808 is fabricated in MITEL’s ISO-
CMOS technology providing low power dissipation
and high reliability. The device contains a 8 x 8 array
of crosspoint switches along with a 6 to 64 line
decoder and latch circuits. Any one of the 64
switches can be addressed by selecting the
appropriate six address bits. The selected switch can
be turned on or off by applying a logical one or zero
to the DATA input. V
SS
is the ground reference of
the digital inputs. The range of the analog signal
is from V
DD
to V
EE
.
Applications
•
•
•
•
•
•
Key systems
PBX systems
Mobile radio
Test equipment /instrumentation
Analog/digital multiplexers
Audio/Video switching
STROBE
DATA RESET
VDD
VEE
VSS
1
AX0
1
••••••••••••••••
AX1
AX2
AY0
AY1
AY2
64
64
8 x 8
6 to 64
Decoder
Latches
Switch
Array
Xi I/O
(i=0-7)
•••••••••••••••••••
Yi I/O (i=0-7)
Figure 1 - Functional Block Diagram
3-15
MT8808
ISO-CMOS
AY2
STROBE
VEE
DATA
VSS
X0
X2
X4
X6
RESET
Y7
Y6
Y5
Y4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AY1
AY0
AX2
AX1
AX0
X1
X3
X5
X7
VDD
Y0
Y1
Y2
Y3
4
3
2
1
28
27
26
•
DATA
VEE
STROBE
AY2
AY1
AY0
AX2
28 PIN CERDIP/PLASTIC DIP
Figure 2 - Pin Connections
Pin Description
Pin #
1
2
Name
AY2
AY2 Address Line (Input).
Description
STROBE
STROBE (Input):
enables function selected by address and data. Address must be stable
before STROBE goes high and DATA must be stable on the falling edge of the STROBE.
Active High.
V
EE
DATA
V
SS
X0, X2,
X4, X6
RESET
Y7 - Y0
V
DD
X7, X5,
X3, X1
AX0-
AX2
Negative Power Supply.
DATA (Input):
a logic high input will turn on the selected switch and a logic low will turn off
the selected switch. Active High.
Digital Ground Reference .
X0, X2, X4 and X6 Analog (Inputs/Outputs):
these are connected to the X0, X2, X4 and
X6 rows of the switch array.
Master RESET (Input):
this is used to turn off all switches. Active High.
Y7 - Y0 Analog (Inputs/Outputs):
these are connected to the Y0 - Y7 columns of the
switch array.
Positive Power Supply.
X7, X5, X3 and X1 Analog (Inputs/Outputs):
these are connected to the X7, X5, X3 and
X1 rows of the switch array.
AX0 - AX2 Address Lines (Inputs).
3
4
5
6-9
10
11-18
19
20-23
24-26
27,28
AY0, AY1
AY0 and AY1 Address Lines (Inputs).
3-16
Y6
Y5
Y4
Y3
Y2
Y1
Y0
12
13
14
15
16
17
18
VSS
X0
X2
X4
X6
RESET
Y7
5
6
7
8
9
10
11
25
24
23
22
21
20
19
AX1
AX0
X1
X3
X5
X7
VDD
28 PIN PLCC
ISO-CMOS
Functional Description
The MT8808 is an analog switch matrix with an array
size of 8 x 8. The switch array is arranged such that
there are 8 columns by 8 rows. The columns are
referred to as the Y inputs/outputs and the rows are
the X inputs/outputs. The crosspoint analog switch
array will interconnect any X I/O with any Y I/O when
turned on and provide a high degree of isolation
when turned off. The control memory consists of a 64
bit write only RAM in which the bits are selected by
the address inputs (AY0-AY2, AX0-AX2). Data is
presented to the memory on the DATA input. Data is
asynchro-nously written into memory whenever the
STROBE input is high and is latched on the falling
edge of STROBE. A logical “1” written into a memory
cell turns the corresponding crosspoint switch on
and a logical “0” turns the crosspoint off. Only the
crosspoint switches corresponding to the addressed
memory location are altered when data is written into
memory. The remaining switches retain their
previous states. Any combination of X and Y inputs/
outputs can be interconnected by establishing
appropriate patterns in the control memory.
A
logical “1” on the RESET input will asynchronously
return all memory locations to logical “0” turning off
all crosspoint switches. Two voltage reference pins
(V
SS
and V
EE
) are provided for the MT8808 to
enable switching of negative analog signals. The
range for digital signals is from V
DD
to V
SS
while the
range for analog signals is from V
DD
to V
EE
. V
SS
and V
EE
pins can be tied together if a single voltage
reference is needed.
MT8808
Address Decode
The six address inputs along with the STROBE are
logically ANDed to form an enable signal for the
resettable transparent latches. The DATA input is
buffered and is used as the input to all latches. To
write to a location, RESET must be low while the
address and data are set up. Then the STROBE
input is set high and then low causing the data to be
latched. The data can be changed while STROBE is
high, however, the corresponding switch will turn on
and off in accordance with the DATA input. DATA
must be stable on the falling edge of STROBE in
order for correct data to be written to the latch.
3-17
MT8808
ISO-CMOS
Absolute Maximum Ratings
*
- Voltages are with respect to V
EE
unless otherwise stated.
Parameter
1
2
3
4
5
6
Supply Voltage
Analog Input Voltage
Digital Input Voltage
Current on any I/O Pin
Storage Temperature
Package Power Dissipation
PLASTIC DIP
CERDIP
Symbol
V
DD
V
SS
V
INA
V
IN
I
T
S
P
D
P
D
-65
Min
-0.3
-0.3
-0.3
V
SS
-0.3
Max
15.0
V
DD
+0.3
V
DD
+0.3
V
DD
+0.3
±15
+150
0.6
1.0
Units
V
V
V
V
mA
°C
W
W
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions
- Voltages are with respect to V
EE
unless otherwise stated.
Characteristics
1
2
3
4
Operating Temperature
Supply Voltage
Analog Input Voltage
Digital Input Voltage
Sym
T
O
V
DD
V
SS
V
INA
V
IN
Min
-40
4.5
V
EE
V
EE
V
SS
Typ
25
Max
85
13.2
V
DD
-4.5
V
DD
V
DD
Units
°C
V
V
V
V
Test Conditions
DC Electrical Characteristics
†
-
Characteristics
1
Quiescent Supply Current
Voltages are with respect to V
EE
=V
SS
=0V, V
DD
=12V unless otherwise stated.
Sym
I
DD
Min
Typ
‡
1
0.4
5
Max
100
1.5
15
±500
0.8+V
SS
Units
µA
mA
mA
nA
V
V
V
Test Conditions
All digital inputs at V
IN
=V
SS
or
V
DD
All digital inputs at V
IN
=2.4 +
V
SS
; V
SS
=7.0V
All digital inputs at V
IN
=3.4V
IV
Xi
- V
Yj
I = V
DD
- V
EE
See Appendix, Fig. A.1
V
SS
=7.5V; V
EE
=0V
V
SS
=6.5V; V
EE
=0V
All digital inputs at V
IN
= V
SS
or V
DD
2
3
4
5
6
Off-state Leakage Current
(See G.9 in Appendix)
Input Logic “0” level
Input Logic “1” level
Input Logic “1” level
Input Leakage (digital pins)
I
OFF
V
IL
V
IH
V
IH
I
LEAK
2.0+V
SS
±1
3.3
0.1
10
µA
† DC Electrical Characteristics are over recommended temperature range.
‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
DC Electrical Characteristics- Switch Resistance
- V
DC
is the external DC offset applied at the analog I/O pins.
Characteristics
Sym
25°C
Typ
1 On-state
V
DD
=12V
Resistance V
DD
=10V
V
DD
= 5V
(See G.1, G.2, G.3 in
Appendix)
2 Difference in on-state
resistance between two
switches
(See G.4 in Appendix)
3-18
70°C
Typ
Max
75
85
215
85°C
Typ
Max
80
90
225
Units
Test Conditions
Max
65
75
185
R
ON
45
55
120
Ω
Ω
Ω
V
SS
=V
EE
=0V,V
DC
=V
DD
/2,
IV
Xi
-V
Yj
I = 0.4V
See Appendix, Fig. A.2
∆R
ON
5
10
10
10
Ω
V
DD
=12V, V
SS
=V
EE
=0,
V
DC
=V
DD
/2,
IV
Xi
-V
Yj
I = 0.4V
See Appendix, Fig. A.2
ISO-CMOS
MT8808
AC Electrical Characteristics
†
- Crosspoint Performance
-Voltages are with respect to V
DD
=5V, V
SS
=0V,
V
EE
=-7V, unless otherwise stated.
Characteristics
1
2
3
Switch I/O Capacitance
Feedthrough Capacitance
Frequency Response
Channel “ON”
20LOG(V
OUT
/V
Xi
)=-3dB
Total Harmonic Distortion
(See G.5, G.6 in Appendix)
Feedthrough
Channel “OFF”
Feed.=20LOG (V
OUT
/V
Xi
)
(See G.8 in Appendix)
Crosstalk between any two
channels for switches Xi-Yi and
Xj-Yj.
Xtalk=20LOG (V
Yj
/V
Xi
).
(See G.7 in Appendix).
Sym
C
S
C
F
F
3dB
Min
Typ
‡
20
0.2
45
Max
Units
pF
pF
MHz
Test Conditions
f=1 MHz
f=1 MHz
Switch is “ON”; V
INA
= 2Vpp
sinewave; R
L
= 1kΩ
See Appendix, Fig. A.3
Switch is “ON”; V
INA
= 2Vpp
sinewave f= 1kHz; R
L
=1kΩ
All Switches “OFF”; V
INA
=
2Vpp sinewave f= 1kHz;
R
L
= 1kΩ.
See Appendix, Fig. A.4
V
INA
=2Vpp sinewave
f= 10MHz; R
L
= 75Ω.
V
INA
=2Vpp sinewave
f= 10kHz; R
L
= 600Ω.
V
INA
=2Vpp sinewave
f= 10kHz; R
L
= 1kΩ.
V
INA
=2Vpp sinewave
f= 1kHz; R
L
= 10kΩ.
Refer to Appendix, Fig. A.5
for test circuit.
R
L
=1kΩ; C
L
=50pF
4
5
THD
FDT
0.01
-95
%
dB
6
X
talk
-45
-90
-85
-80
dB
dB
dB
dB
7
Propagation delay through
switch
t
PS
30
ns
† Timing is over recommended temperature range. See Fig. 3 for control and I/O timing details.
‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
Crosstalk measurements are for Plastic DIPS only, crosstalk values for PLCC packages are approximately 5dB better.
AC Electrical Characteristics
†
- Control and I/O Timings
- Voltages are with respect
V
EE
=-7V, unless otherwise stated.
to V
DD
=5V, V
SS
=0V,
Characteristics
1
Control Input crosstalk to switch
(for CS, DATA, STROBE,
Address)
Digital Input Capacitance
Switching Frequency
Setup Time DATA to STROBE
Hold Time DATA to STROBE
Setup Time Address to STROBE
Hold Time Address to STROBE
STROBE Pulse Width
RESET Pulse Width
STROBE to Switch Status Delay
DATA to Switch Status Delay
RESET to Switch Status Delay
Sym
CX
talk
Min
Typ
‡
30
Max
Units
mVpp
Test Conditions
V
IN
=3V squarewave;
R
IN
=1kΩ, R
L
=10kΩ.
See Appendix, Fig. A.6
f=1MHz
R
L
= 1kΩ,
R
L
= 1kΩ,
R
L
= 1kΩ,
R
L
= 1kΩ,
R
L
= 1kΩ,
R
L
= 1kΩ,
R
L
= 1kΩ,
R
L
= 1kΩ,
R
L
= 1kΩ,
C
L
=50pF
C
L
=50pF
C
L
=50pF
C
L
=50pF
C
L
=50pF
C
L
=50pF
C
L
=50pF
C
L
=50pF
C
L
=50pF
2
3
4
5
6
7
8
9
10
11
12
C
DI
F
O
t
DS
t
DH
t
AS
t
AH
t
SPW
t
RPW
t
S
t
D
t
R
10
10
10
10
20
40
10
20
pF
MHz
ns
ns
ns
ns
ns
ns
40
50
35
100
100
100
ns
ns
ns
Q
Q
Q
Q
Q
Q
Q
Q
Q
† Timing is over recommended temperature range. See Fig. 3 for control and I/O timing details.
Digital Input rise time (tr) and fall time (tf) = 5ns.
‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
Refer to Appendix, Fig. A.7 for test circuit.
Q
3-19
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