®
MT88V32
8 x 4 High Performance Video Switch Array
Preliminary Information
Features
•
•
•
•
•
•
•
•
•
•
•
32 bidirectional CMOS "T" switches in an 8
×
4
non-blocking array
Break-before-make switching configuration
Fast setup & hold times for switch programming
3dB bandwidth of 200MHz
Low feedthrough and crosstalk, better than -80dB
at 5MHz
Very low differential gain and phase errors
12Vpp bipolar signal capability
On-state resistance 75Ω (max) for V
DD
=+5V,
V
EE
=-7V
Switch control through 2-stage latches
Orthogonal Xi and Yi pin connections for
optimized PCB layout
Latch readback capability for monitoring
ISSUE 1
August 1993
Ordering Information
MT88V32AP
44 Pin PLCC
-40° to 85°C
Each of the 32 nodes of the switching matrix has a T-
switch, see Fig.1. This grounds the nodes of all open
connections, which greatly reduces feedthrough
noise. In order to reduce crosstalk, individual analog
signal lines are isolated by interleaving them with
ground lines.
The two stage programmable latch system allows
the state of all switching nodes to be updated
simultaneously. The next state of the switch is written
into the first stage of the latches through individual
write cycles. These changes will not affect the
current state of the switch. The STROBE2 control
input is used to load the state of all first stage latches
to the second stage latches, which updates the
complete matrix. Therefore, all 32 switching nodes
are updated simultaneously.
The MT88V32 supports separate analog (V
EE
) and
digital (V
DD
) voltage references. This allows the user
to select an optimum analog signal bias point.
Applications
•
•
•
•
High-end video routing and switching
Medical instrumentation
Automatic test equipment (ATE)
Multi-media communication
Description
The MT88V32 is a digitally programmable (TTL levels)
8
×
4 crosspoint switch that is designed to control wide-
band analog (video) signal.
Y0-Y7
VDD VEE VSS
X0
X1
X2
X3
Yi
STROBE2
2nd Stage Latches
I/O
Control
Logic
R/W
DATA
CS
T-Switch Configuration
Address Decode
GND
Xi
GND
MR
8x4
"T" Switch Array
STROBE1
1st Stage Latches
AX0-AX1
AY0-AY2
Figure 1 - Functional Block Diagram
3-51
MT88V32
GND
Y0
GND
GND
X0
GND
X1
GND
X2
GND
X3
Preliminary Information
Y1
GND
Y2
GND
Y3
GND
Y4
GND
Y5
GND
Y6
6 5 4 3 2 1 44 43 42 41 40
7
39
8
38
9
37
10
36
11
35
12
34
13
33
14
32
15
31
16
30
29
17
18 19 20 21 22 23 24 25 26 27 28
GND
Y7
GND
VEE
IC*
VDD
VSS
AX1
AX0
AY2
NC
GND
NC
MR
STROBE2
STROBE1
R/W
CS
DATA
AY0
AY1
NC
* Connects toV
EE
Figure 2 - Pin Connections
Pin Description
Pin #*
1, 3, 4, 6,
8, 10,
12, 14,
16, 18,
20, 39,
41, 43
2, 44,
42, 40
5, 7,
9, 11,
13, 15,
17, 19
21
22
23
24
25, 26
27, 30,31
28, 29
32
Name
GND
Description
Analog Ground.
Connect to system ground for crosstalk noise isolation. Pins 3 and 39
are not bonded internally.
X0, X1,
X2, X3
Y0, Y1,
Y2, Y3
Y4, Y5,
Y6, Y7
V
EE
IC
V
DD
V
SS
AX1,AX0
AY2-AY0
NC
DATA
Analog Lines (input/output).
Analog Lines (input/output).
Negative Analog Power Supply.
Internal Connection.
Positive Power Supply.
Digital Ground Reference.
X0-X3 I/O Address Select (inputs).
Y0-Y7 I/O Address Select (inputs).
No Connection.
DATA (input/output).
When input, a logic high will close the selected switch and a logic
low will open the selected switch. When output, a logic high indicates a closed switch
and a logic low indicates an opened switch.
Chip Select (input).
Active low.
READ/WRITE Control (input).
When high the DATA pin is an output (for reading from
second stage latch); when low the DATA pin is an input (for writing to first stage latch).
33
34
35
CS
R/W
STROBE1
STROBE 1 (input).
Modifies memory content of first stage latch as determined by the
addess and data lines, but does not change the switch array configuration of entire
switch array. Active low.
STROBE2
STROBE 2 (input).
Transfers memory content of first stage latch to the second stage
latch and hence, changes the configuration of entire switch array. Active low.
MR
NC
MASTER RESET (input).
Used to reset the first and second stage latches. Active low.
No Connection.
36
37
38
3-52
Preliminary Information
Functional Description
The state of the MT88V32 8 X 4 switching matrix is
updated through a simple parallel processor
interface. This interface provides access to 32 two
stage latches, which determines the state (open/
close) of each switching array node. Each latch (or
node) is addressed by the AX0-AX1 and AY0-AY2
inputs as per Table 2, and the DATA input will
determine if the connection is to be made (DATA=1)
or opened (DATA=0).
The second stage of the two stage latches controls
the current state of each switching node. The value
held in the first stage is the input to the second
stage. This allows the device to be programmed in
two ways. That is, individual switching nodes may be
updated one at a time, or all nodes may be updated
at once.
To update one node at a time the STROBE2 input
should be held low. This makes the second stage
latches transparent and the matrix immediately
reflects the state of the first stage latches. A write
cycle example follows:
1)
2)
3)
4)
5)
STROBE2 is low,
CS and R/W are low, MR is high,
AX0-AX1 and AY0-AY2 as per Table 2,
DATA input high to close or low to open, and
STROBE1 toggled from high-to-low-to-high.
MT88V32
These steps (one write cycle) may be repeated for
each switch state change. This can also be
accomplished by holding STROBE1 low and toggling
STROBE2. See Figure 14 for timing.
To update all nodes simultaneously all switch state
changes must be written into the first stage latches.
This is accomplished by holding STROBE2 high and
performing steps 2) through 5) above for each
switching node that is to be changed. Writing to the
first stage latches only will not affect the switching
state of the matrix. When the changes have been
made all the switches of the matrix may be updated
simultaneously by toggling the STROBE2 input from
high-to-low-to high.
When STROBE2 is used to update the state of the
MT88V32 all switch “breaks” are completed before
any switch “makes” occur. There is approximately
10ns delay between “breaks” and “makes”.
Both the first and second stage latches will be
cleared when the master reset (MR) is taken from
high-to-low. This will open all the switch nodes. The
operation of MR is independent of CS, AX0-AX1,
AY0-AY2 and R/W.
The status of each switching array node (second
stage latch) can be read through the bidirectional
DATA pin. A read cycle example follows:
1) CS is low, R/W and MR are high,
2) AX0-AX1 and AY0-AY2 as per Table 2, and
3) DATA output high for closed or low for open.
STROBE2
DATA
MR
R/W
CS
DATA
STROBE1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
x
x
0
0
0
1
0
1→
0→
1
1
x
x
x
0
1→
0
1→
0
0
0
0→
1
1
1
0
x
1
1
1
1
1
1→
0
0→1
0
x
No Change to 1st stage latch.
1st stage latch is loaded with data.
1st stage latch is transparent.
Selected latch is cleared and set again (i.e.,
output follows input).
1st stage latch output is frozen.
Output of 1st stage latch is transferred to
output of 2nd stage latches.
2nd stage latch output is frozen.
Both 1st stage and 2nd stage latches are
transparent.
DATA becomes an output and reflects the
contents of the 2nd stage latch addressed
by AX0-AX1 and AY0-AY2.
All crosspoints opened (data in 1st and 2nd
stage latches are cleared).
0
1
1
1
1
1
T
able 1 - Truth Tables
Note: x = don’t care, 0 = logic "0" state, 1 = logic "1" state
A logic 1 on DATA input closes a connection.
A logic 0 on DATA input opens a connection.
3-53
MT88V32
AX1
AX0
AY2
AY1
AY0
Preliminary Information
Switch Connections
0
0
0
0
0
0
0
0
0
↓
0
1
↓
1
1
↓
1
0
0
0
0
0
0
0
0
1
↓
1
0
↓
0
1
↓
1
0
0
0
0
1
1
1
1
0
↓
1
0
↓
1
0
↓
1
0
0
1
1
0
0
1
1
0
↓
1
0
↓
1
0
↓
1
0
1
0
1
0
1
0
1
0
↓
1
0
↓
1
0
↓
1
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
to
to
to
to
to
to
to
to
X0
X0
X0
X0
X0
X0
X0
X0
Y0 to X1
↓
Y7 to X1
Y0 to X2
↓
Y7 to X2
Y0 to X3
↓
Y7 to X3
T
able 2 - Address Decode Truth Table
It should be noted that the STROBE1 function is
disabled during a read cycle. See Fig. 15 for timing.
The MT88V32 can operate from a dual rail power
supply (V
DD
and V
EE
) or a single rail power supply
(V
SS
=V
EE
=0V) as per the recommended operating
conditions. For minimum on-state resistance the
supply voltages should be V
DD
=5.0 V
DC
, V
SS
=0 V
DC
and V
EE
=-7 V
DC
. The analog input signal should be
biased at -2.0 V
DC
to achieve minimum differential
phase and gain error (see AC Electrical
Characteristics - Crosspoint Performance).
ground (R) should be present between the switches.
Selection of R is based on the following compromise:
1) as R is decreased to approach the source and
terminating resistance values signal loss will
increase and crosstalk will decrease, and
2) as R increases signal loss will decrease and
crosstalk will increase.
It is recommended that the power supply rails of the
MT88V32 be decoupled with 0.1µF ceramic Z5U and
10µF dipped tantalum capacitors. These capacitors
should be as close to the device as possible. The
signal pins of the MT88V32 are interleaved with
analog ground lines. This allows the circuit designer
to run ground tracks on both sides of each signal line
to improve crosstalk immunity.
The 8x4 bidirectional CMOS T-switch configuration is
a modular switching element in a convenient
package size. The inherent flexibility of this device
permits the designer to build large switching
matrices, see analog switch application notes.
A
5
A
4
A
3
A
2
A
1
A
0
D
0
Function
Applications
Figure 3 illustrates examples of how to connect the
signal lines of the MT88V32 to various interfaces.
Input buffers allow the incoming signals to be scaled
and biased to the optimum operating range of the
MT88V32 (i.e., differential phase error, differential
gain error and R
ON
). Buffers will also allow a more
precise input impedance to be implemented. For low
grade video applications, signal lines may be
connected directly, as long as the ultimate source
and terminating impedances are matched.
Output buffers may be used to provide signal gain
and impedance matching for external connections.
Additionally, they may be used to isolate parasitic
device capacitance in multiple stage switching
applications where high frequency roll-off is critical.
Crosstalk, as well as differential phase and gain error
can be minimized by designing a low source
impedance (e.g., 10 ohms), and a high terminating
impedance (e.g., 10k) at each stage. If successive
switching stages are not buffered, then a resistor to
3-54
0
↓
0
↓
0
↓
0
↓
0
↓
0
↓
1/0
↓
Y0 to X0
↓
↓
0
1
1
1
X
X
1
X
X
1
X
X
1
X
X
1
0
1
1/0
X
X
Y7 to X3
MR
STB2
Table 3 - Address Decoding for the Processor
Interfaces
Note: x = undefined, 1/0 -1 = make, 0 = break
Preliminary Information
MT88V32
Wideband
Output Buffers
75Ω
10kΩ
Wideband
Input Buffers
10kΩ
75Ω
75Ω
MT88V32
X0
X1
X2
X3
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
10kΩ
75Ω
75Ω
Wideband
Output Buffers
75Ω
10kΩ
Control Interface
10kΩ
To next
switching
stage
10kΩ
R
Figure 3 - High Frequency Switching Applications
Figures 4, 5 and 6 show methods of interfacing the
MT88V32 to Motorola and Intel microcontrollers. The
address decoding for these configurations is in Table
3.
Video Signal Terminology
1) Component Video - separate red (R), blue (B),
green (G), and synchronization signals.
2) Composite
Video
-
contains
luminance
(brightness),
chrominance
(colour),
and
synchronization signal components in a single
waveform.
3) Synchronization signal - horizontal sync pulses
are negative going excursions of the composite
video signal that occur every 63.5 µsec. Their
function is to align the horizontal sweep.
Vertical synchronization is achieved during the
vertical blanking interval, which is about 1200
µsec or 20 horizontal scan intervals long. It
consists of a number of vertical synchronization
and equalization pulses.
4) Luminance - is the black to white brightness
component of a composite video signal. Its range
is from reference white (maximum amplitude) to
reference black (minimum amplitude).
5) Chrominance - rides on the luminance signal and
determines the hue (phase) and brightness
(amplitude) of the colour component of a
composite video signal.
6) Colour burst - is about 9 (minimum 8) cycles of a
3.578545 MHz reference signal, which is
transmitted with every horizontal sweep of the
composite video signal. A phase comparison
3-55
NXP MCU
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