®
CMOS
MT9080
SMX - Switch Matrix Module
Features
•
•
•
•
•
•
•
Timeslot interchange circuit for digital switch
applications
16 bit wide data bus I/O
2048 x 16 bit wide byte capacity
Dual addressing capability; internal counter
and external address bus
Variable clock and frame rates
Microprocessor interface
CMOS
ISSUE 3
January 1993
Ordering Information
MT9080AP
84 Pin PLCC
-40°C to 70°C
Description
The MT9080 is a flexible memory module suitable for
use as a basic building block in the construction of
large digital switching matrices. It can be configured
as either a Data Memory or a Connection Memory.
Interface to the device is via 16 bit wide data and
address busses. The MT9080 can operate with
variable clock rates up to 16.7 MHz.
Applications
•
Building block for digital switching matrices
used in PBXs, CO equipment, data switching,
etc.
Programmable delay lines
•
D0i/D15i
16
16
2048 x 16
16
Address
MUX
11
11 Bit
Counter
WR
ENABLE
PRECHARGE
Static
Memory
16
D0o/
D15o
A0-A15
CRC
CD
Control Interface
Counter
Reset
ME
FP
CK
ODE DS
CS R/W
Mx
My
Mz
DTA
Figure 1 - Functional Block Diagram
2-101
MT9080
CMOS
D15o
D14o
D13o
D12o
D10o
D11o
VDD
VSS
VSS
VSS
VSS
D9o
76
10
8
6
4
2
84
82
80
D8i
D9i
D10i
D11i
VSS
D12i
D13i
D14i
D15i
VSS
CK
VDD
VSS
IC
IC
FP
CS
DS
R/W
DTA
NC
78
D8o
D7i
D6i
D5i
D4i
D3i
D2i
D1i
D0i
12
14
16
18
20
22
24
26
28
30
74
72
70
68
66
VSS
D7o
D6o
D5o
D4o
VSS
D3o
D2o
D1o
D0o
VSS
VDD
CD
A15
A14
A13
A12
A11
A10
A9
A8
84 PIN PLCC
64
62
60
58
56
46
48
34
36
38
40
42
44
50
32
52
A5
54
NC
NC
VDD
NC
IC
IC
A0
A1
A2
A3
A4
A6
ODE
VSS
Figure 2 - Pin Connections
Pin Description
Pin #
1
2-5
Name
V
SS
D0i-D3i
Ground.
Input/Microport Data Bus.
This is part of a 16 bit data bus. The data bus is bidirectional in
Connect Memory mode where it is typically interfaced to a microprocessor. In all other
modes the data bus is an input. Data to be switched through the device is clocked in at this
port.
Ground.
Input/Microport Data Bus.
See description for pins 2-5 above.
Ground.
Description
6
7-10
11
12-15
16
17-20
21
22
23
24
25,26
27
V
SS
D4i-D7i
V
SS
D8i-D11i Input/Microport Data Bus.
See description for pins 2-5 above.
V
SS
Ground.
See description for pins 2-5 above.
D12i-D15i Input/Microport Data Bus.
V
SS
CK
V
DD
V
SS
IC
FP
Ground.
Clock.
Master clock input which is used to clock data into and out of the device. It also
clocks the internal 11 bit counter.
+5V supply input .
Ground.
Internal Connection.
Should be tied to V
SS
for normal operation.
Frame Pulse.
An active low signal that serves as a synchronous clear for the internal 11 bit
counter in all modes except Shift Register mode. The counter is cleared on a rising edge of
CK. In the Shift Register mode, FP serves to align channel boundaries.
2-102
VSS
ME
Mx
My
Mz
A7
CMOS
Pin Description
Pin #
28
Name
CS
Description
MT9080
Chip Select.
Active Low input. Selects the device for microport access in connect memory,
data memory, external and shift register modes. Tying CS high will disable output data
drivers (D0-D15o) in all modes except connect memory and shift register modes.
Data Strobe.
Active low input. Indicates to the SMX that valid data is present on the
microport data bus during a write operation or that the SMX must output data on a read
operation.
In Connect Memory modes, a low level applied to this input during a write operation indicates
to the SMX that valid data is present on the microport data bus. During a read operation the
low going signal indicates to the SMX that it must output data on the microport data bus.
In Data Memory and External modes, when DS is high, the output data bus D0o-D15o will be
disabled. The input data bus D0i-D15i is not affected.
The DS input has no effect on the input and output busses in Counter or Shift Register
modes.
Read/Write Enable.
Data is written into the device when R/W is low and read from it when it
is high. This control input is disabled in data memory and shift register modes. It should be
tied to V
SS
or V
DD
in these modes. In counter and external modes, the state of R/W pin is
clocked in with the rising edge of CK. The actual read or write operation will be implemented
on the next rising clock edge.
Data Transfer Acknowledge.
Open drain output which is pulled low to acknowledge
completion of microport data transfer. On a read of the SMX, DTA low indicates that the
SMX has put valid data on the data bus. On a write, DTA low indicates that the SMX has
completed latching the data in.
No Connection.
Ground.
No Connection.
Output Data Enable.
Control input which enables the output data bus. Pulling this input low
will place the data bus in a high impedance state. The level on this pin is latched by a rising
edge of CK. The output drivers will be enabled or disabled with the rising edge in the next
timeslot (see Fig. 24 for applicable timing in different modes).
Message Enable.
When tied high the data latched in on the address bus is clocked out on
D0o-D15o. When ME is tied low, the contents of the addressed memory location will be
output on the bus. The level on this pin is latched in with the rising edge of the clock. The
actual mode change is implemented on the rising edge in the next timeslot. Refer to Figures
25 and 26 for more timing information.
Mode X.
One of three inputs which permit the selection of different operating modes for the
device. Refer to Table 1 for description of various modes.
Mode Y.
See description for pin 37.
Mode Z.
See description for pin 37.
No Connection.
Internal Connection.
Leave open for normal operation.
Ground.
Supply Voltage. +5V .
No Connection.
29
DS
30
R/W
31
DTA
32
33
34
35
NC
V
SS
NC
ODE
36
ME
37
38
39
40
41, 42
43
44
45
Mx
My
Mz
NC
IC
V
SS
V
DD
NC
2-103
MT9080
CMOS
Pin Description
Pin #
46-61
Name
A0-A15
Description
Address Bus.
These inputs have three different functions. Inputs A0-A10 are used to
address internal memory locations during read or write operations in all modes except Shift
Register mode. In Shift Register mode, the levels latched in on A0-A10 program the delay
through the device. When the ME pin is tied high, the data latched in on A0-A15 is clocked
out on to the data bus (D0o-D15o).
Change Detect.
Open drain output which is pulled low when a change in the memory
contents from one frame to the next is detected by a Cyclic Redundancy Check (CRC).
Changes in memory contents resulting from microprocessor access do not cause CD to go
low. The output is reset to its normal high impedance state when the DS input is strobed,
while the device has been selected (CS is low).
Supply Voltage. +5V .
Ground.
62
CD
63
64
65-68
V
DD
V
SS
D0o-D3o Output Data Bus.
These three state outputs are part of a 16 bit data bus which is used to
clock out data from the device. Data is clocked out with the rising edge of the clock. See
Figures 24 to 26 for timing information. The bus is actively driven when ODE is tied high. It
is disabled when ODE is tied low. Tying CS high will also disable the output data bus in all
modes except Connect Memory and Shift Register Modes.
V
SS
Ground.
69
70-73
74
75-78
79
80-83
84
D4o-D7o Output Data Bus.
See description for pins 65-68.
V
SS
Ground.
D8o-D11o Output Data Bus.
See description for pins 65-68.
V
SS
Ground.
D12o-D15 Output Data Bus.
See description for pins 65-68.
o
V
DD
Supply Voltage. +5V .
2-104
CMOS
Functional Description
The SMX is a flexible memory module suitable for
use in the construction of timeslot interchange
circuits used in PCM voice or data switches. The
device can be configured as a data memory or a
connection memory.
The SMX has separate 16 bit input and output data
busses.
A 16 bit address bus and a full
microprocessor interface is also provided.
Data is clocked into and out of the device with the
signal applied at the CK (clock) input. Depending on
the mode of operation, the memory locations for the
read or write operation can be addressed
sequentially by the internal counter or randomly via
the external address bus. A messaging sub-mode,
which permits the data latched in on the address bus
to be multiplexed on to the output data bus, is also
available (see ME pin description).
The SMX ensures integrity of the stored data by
performing a Cyclic Redundancy Check (CRC) on a
per frame basis. When a change in the memory
contents is detected from one frame to the next, the
Change Detect (CD) pin is pulled low. The output
will be reset to its normal high impedance state when
DS input is strobed while CS is low (i.e., while the
device has been selected for microprocessor
access). The CD output is not pulled low when the
memory contents have been modified by a processor
access to the device.
Modes Of Operation
The SMX can be programmed to operate in one of
eight modes as summarized in Table 1. The different
modes are used to realize specific switch
implementations. For example, to implement a 1024
channel switch, two SMXs are required. One is
operated in Data Memory mode, while the second is
operated in Connect Memory mode. A 2048 channel
switch can be realized using three SMXs. Two of the
devices are operated, alternatively, in Counter and
External modes, the third serves as the Connection
Memory.
A detailed description
of the
implementation is presented in the Applications
section of this data sheet. An outline of the device
functionality in each mode is presented below.
Mode
1
2
3
4
5
6
7
8
M
X
0
0
0
0
1
1
1
1
M
Y
0
0
1
1
0
0
1
1
M
Z
0
1
0
1
0
1
0
1
Name
Data Memory - 1
Data Memory - 2
Connect Memory - 1
Connect Memory - 2
Counter Mode
External Mode
Shift Register Mode
Data Memory - 3
Abbr.
DM-1
DM-2
CM-1
CM-2
CNT
EXT
SR
DM-3
MT9080
Data Memory Mode-1
Data Memory Mode-1 is designed for use in the
construction of a 1024 Channel Switch Matrix. Data
on the D0-D15 input bus is clocked into the SMX and
stored in memory locations addressed by the internal
11 bit counter. Data is clocked out according to the
addresses asserted on the address bus. The pin
configuration of the device in this mode is illustrated
in Fig .3
CK
Data
Input
16
FP
Data
Output
D0
i
-D15
i
D0
o
-D15
o
16
CS
DS
CD
DTA
MODE
A0-A15
ME
ODE Z
Y
Z
From Control Interface
Fig. 3 - Data Memory Modes 1 and 2 Pinout
The timing for the read and write operation is
illustrated in Fig. 4. The first half of each clock period
is used for precharging the internal bus. Data is
latched in and out of the device with rising edge of
the CK clock. Correct operation of the device in this
mode requires 2048 clock cycles in a single frame
defined by the frame pulse. Consequently, for
switching of 64 kbit/s PCM voice channels, the clock
frequency must be 16.384 Mbit/s with a frame rate of
8 kHz.
The address supplied on the address bus is latched
in with the first positive clock edge in a channel
timeslot. The contents of the memory location
addressed will be clocked out on D0-D15o with the
first positive clock edge in the next timeslot (see Fig.
4).
In Data Memory Mode-1, the delay through the
switch depends on the number of channel timeslots
between the input channel and the output channel. If
the time difference between the input channel and
output channel is less than two channels, data
clocked into the device in the current frame will be
clocked out in the next frame. If the difference is
greater than or equal to two channels, data will be
clocked out in the same frame.
This concept is
further illustrated in Fig. 5.
2-105
Table 1. SMX Modes of Operation
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