®
CMOS
MT90810
Flexible MVIP Interface Circuit
Preliminary Information
Features
•
•
MVIP
™
and ST-BUS
™
compliant
MVIP Enhanced Switching with 384x384
channel capacity (256 MVIP channels; 128
local channels)
On-chip PLL for MVIP master/slave operation
Local output clocks of 2.048,4.096,8.192MHz
with programmable polarity
Local serial interface is programmable to
2.048, 4.096, or 8.192Mb/s with associated
clock outputs
Additional control output stream
Per-channel message mode
Two independently programmable groups of up
to 12 framing signals each
Motorola non-multiplexed or Intel multiplexed/
non-multiplexed microprocessor interface
MT90810AK
ISSUE 2
October 1994
Ordering Information
100 Pin PQFP
0 °C to +70 °C
•
•
•
Description
Mitel’s MT90810 is a Flexible MVIP Interface Circuit
(FMIC). The MVIP (Multi-Vendor Integration
Protocol) compliant device provides a complete
MVIP compliant interface between the MVIP Bus and
a wide variety of processors, telephony interfaces
and other circuits. A built-in digital time-slot switch
provides MVIP enhanced switching between the full
MVIP Bus and any combination of up to 128 full
duplex local channels of 64kbps each. An 8 bit
microprocessor port allows real-time control of
switching and programming of device configuration.
On-board clock circuitry, including both analog and
digital phase-locked loops, supports all MVIP clock
modes. The local interface supports PCM rates of
2.048, 4.096 and 8.192Mb/s, as well as parallel DMA
through the microprocessor port.
•
•
•
•
•
Applications
•
•
•
•
•
Medium size digital switch matrices
MVIP interface functions
Serial bus control and monitoring
Centralized voice processing systems
Voice/Data multiplexer
EX_8KA
EX_8KB
X2
X1/CLKIN PLL_LO
PLL_LI
FRAME
SEC8K
C4b
C2o
F0b
DSo[0:7]
DSi[0:7]
LDO[0:3]
LDI[0:3]
TCK
TMS
TDI
TDO
Timing and Clock Control
(Oscillator and Analog & Digital PLLs)
Enhanced Switch
S-P/
P-S
Data Memory
Connection Memory
Programmable
Framing Signals
CLK2
CLK4
CLK8
RESET
CSTo
FGA[0:11]
FGB[0:11]
JTAG
Microprocessor Interface
ERR
AD[0:7] A[0:1] ALE
WR/
R/W
RD/
DS
CS
RDY/ DREQ[0:1] DACK[0:1]
DTACK
Figure 1 - Functional Block Diagram
2-145
MT90810
Preliminary Information
SEC8K
VSS
52
FGB9
DSi6
FGA9
FGB8
DSi1
FGA8
C4b
LDO0
VSS
FGA10
LDO1
LDO2
FGB10
LDO3
VDD
LDI0
LDI1
LDI2
LDI3
EX8_KA
EX8_KB
VSS
FRAME
CLK8
FGA11
CLK4
CLK2
FGB11
FGA0
80
82
78
76
74
72
70
68
66
64
62
60
58
56
54
FGB7
50
48
DSo7
DSo6
DSo5
DSi4
DSo4
DSo3
VSS
DSo2
DSo1
DSo0
DSi7
DSi5
DSi3
DSi2
DSi0
VDD
C2o
F0b
DREQ1
DREQ0
DACK1
DACK0
FGA7
AD7
AD6
AD5
AD4
VSS
VDD
FGB6
AD3
AD2
AD1
AD0
A1
FGA6
A0
ERR
84
46
86
44
88
42
90
92
94
36
96
34
98
32
100 2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
40
38
100 PIN PQFP
X1/CLKIN
RESET
FGA5
VCO_VDD
WR/[R/W]
VDD
VSS
TCK
TDI
PLL_LI
FGA1
FGA2
FGA3
CSTo
FGA4
FGB0
FGB1
FGB2
FGB3
FGB4
RD/[DS]
FGB5
ALE
Figure 2 - Pin Connections
2-146
RDY/[DTACK]
X2
VCO_VSS
TMS
TDO
PLL_LO
CS
Preliminary Information
MT90810
Pin Description
Pin #
58, 60, 63, 67, 70,
72, 74, 77
59, 61, 64, 68, 71,
73, 75, 78
80, 82, 83, 85
87, 88, 89, 90
4
Name
DSo[0:7]
DSi[0:7]
LDO[0:3]
LDI[0:3]
CSTo
Description
MVIP DSo Streams
(Bidirectional CMOS). 2.048Mb/s serial data
streams conforming to ST-BUS serial data stream specifications.
MVIP DSi Streams
(Bidirectional CMOS). 2.048Mb/s serial data
streams conforming to ST-BUS serial data stream specifications.
Local Output Serial Streams
(Output). Serial data streams
programmable to 2.048, 4.096 or 8.192Mb/s data rates.
Local Input Serial Streams
(TTL Input). Serial data streams
programmable to 2.048, 4.096 or 8.192 Mb/s data rates.
Control ST-BUS Output
(Output). This is a 1.024Mb/s output. The
state of each bit in this stream is determined by the CSTo bit in
connection memory high.
MVIP F0 signal
(CMOS Input/Output). ST-BUS 8kHz framing signal
MVIP C4 signal
(CMOS Input/Output). ST-BUS 4.096MHz clock
MVIP C2 signal
(Output). ST-BUS 2.048MHz clock. This pin is
automatically set to high impedance when it is not driven.
MVIP SEC8K signal
(CMOS Input/Output). A secondary 8kHz signal
used either as an input source to the on-chip digital PLL or as an
output to the MVIP bus.
External 8kHz input A
(TTL Input).
External 8kHz input B
(TTL Input).
Local Frame Output Signal
(Output). This 8kHz framing signal has a
duty cycle and period equal to the MVIP F0 signal.
8MHz Local Output Clock
(Output). This is a 8MHz clock.
4MHz Local Output Clock
(Output). This 4MHz clock has a duty
cycle and period equal to the MVIP C4 signal.
2MHz Local Output Clock
(Output). This 2MHz clock has a duty
cycle and period equal to the MVIP C2 signal.
Frame Group A framing signals
(Output). Programmable framing
signals. The frame group outputs are determined by mode bits in the
frame register to be either programmed outputs, output drive enables
for DSo, or output framing pulses for use with local serial data
streams.
Frame Group B framing signals
(Output). Programmable framing
signals. The frame group outputs are determined by mode bits in the
frame register to be either programmed outputs, output drive enables
for DSi, or output framing pulses for use with local serial data streams.
Chip Reset
(Schmitt Input). This active low reset clears all internal
registers, connection memory and data memory
Microprocessor Address/Data Bus
(Bidirectional TTL).
Microprocessor access to internal registers, connection and data
memories.
In non-multiplexed mode: data bus.
In multiplexed mode: multiplexed address and data bus.
55
56
54
53
F0b
C4b
C2o
SEC8K
91
92
94
95
97
98
100, 1, 2, 3, 5, 20,
33, 46, 57, 69, 81,
96
EX_8KA
EX_8KB
FRAME
CLK8
CLK4
CLK2
FGA[0:11]
6, 7, 8, 9, 14, 28,
39, 51, 62, 76, 84,
99
19
35, 36, 37, 38, 42,
43, 44, 45
FGB[0:11]
RESET
AD[0:7]
2-147
MT90810
Pin Description
Pin #
32, 34
Name
A[0:1]
Preliminary Information
Description
Microprocessor Address
(TTL Input).
In non-multiplexed mode: address to FMIC internal registers
In multiplexed mode: unused (leave unconnected).
29
ALE
Microprocessor Address Latch Enable
(TTL Input). Selects the
microprocessor mode.
In Intel multiplexed mode, the falling edge of this signal is used to
sample the address.
27
CS
Microprocessor Bus Chip Select
(TTL Input). This active low input
enables microprocessor access to connection and data memory and
internal registers.
Read/Data Strobe
(TTL Input).
In Intel mode (RD), this active low input configures the data bus lines
as output.
In Motorola mode (DS), this active low input operates with CS to
enable read and write operation.
26
RD/ [DS]
25
WR/ [R/W]
Write\ Read/Write Strobe
(TTL Input).
In Intel mode (WR), this active low input configures the data bus lines
as inputs.
In Motorola mode (R/W), this input controls the direction of the data
bus D[0:7] during a microprocessor access.
30
RDY [DTACK]
Ready/Data Acknowledge
(Open Drain Output).
In Intel mode (RDY), this output acts as IOCHRDY. A 10K pull up is
required.
In Motorola mode (DTACK), this active low output indicates a
successful data bus transfer. A 10K pull up is required.
31
49, 50
ERR
DREQ[0:1]
Error Status
(Output). This pin is asserted high if either a clock error
(loss of C4b clock), DMA overrun condition or PLL unlock occurs.
DMA Request
(Output). When DMA operations on the device are
enabled, this pin requests transfers for DMA reads/writes from/to the
device.
DMA Acknowledge
(TTL Input). When DMA operations on the device
are enabled, this pin receives acknowledgement for DMA reads/writes
from/to the device.
JTAG Input Clock
(TTL Input). Maximum recommended clock rate is
16 MHz. If not used, this pin should be left unconnected.
JTAG Serial Input Data
(TTL Input). If not used, this pin should be left
unconnected.
47, 48
DACK[0:1]
10
11
TCK
TDI
2-148
Preliminary Information
Pin Description
Pin #
12
13
17
18
22
23
21
24
15, 40, 65, 86
16, 41, 52, 66,
79, 93
Name
TDO
TMS
X1/CLKIN
X2
PLL_LO
PLL_LI
VCO_VSS
VCO_VDD
VDD[0:3]
VSS[0:5]
Description
MT90810
JTAG Serial Output Data
(Output). If not used, this pin should be left
unconnected.
JTAG Mode Control Input
(TTL Input). If not used, this pin should be
left unconnected.
Clock Input Pin/ Crystal Oscillator Pin1.
Crystal Oscillator Pin 2
(Input). If X1 is clock input, this pin should be
left unconnected.
PLL Loop Filter Output.
(Output 6mA drive).
PLL Loop Filter Input.
(1
µA
Low level/High level Input current).
Ground for On-chip VCO.
+5 Volt Power Supply for On-chip VCO.
+5 Volt Power Supply.
Ground.
Device Overview
Mitel’s MT90810 is a MVIP compliant device. It
provides a complete, cost effective, MVIP compliant
interface between the MVIP Bus and a wide variety
of processors, telephony interfaces and other
circuits. The FMIC supports 384 full duplex, time
division multiplexed (TDM), channels. These
channels are divided into 256 full duplex MVIP
channels and 128 full duplex local channels. The
sample rate for each channel is 8kHz and the width
of each channel is 8 bits for a total data rate of
64kbits/s per channel.
The FMIC’s internal clock circuitry includes both an
analog and a digital PLL and supports all MVIP clock
modes. The device can be configured as a timing
master whereby an external 16.384MHz crystal or
4.096, 8.192 or 16.384MHz external clock source is
used to generate MVIP clock signals. The device can
also operate as a slave to the MVIP bus,
synchronizing its master clock to the MVIP 4MHz
bus clock.
The device’s local serial interface supports PCM
rates of 2.048, 4.096 and 8.192Mb/s, per channel
message mode, an additional control stream, as well
as parallel DMA through the microprocessor port.
Furthermore, the FMIC’s programmable group of
output framing signals and local output clocks may
be used to provide the appropriate frame and clock
pulses to drive other local serial buses such as GCI.
A microprocessor interface permits reading and
writing of the data memory, connection memory and
all internal control registers. The Connection and
Data memory can be read and updated while the
MVIP bus is active, that is, connections can be made
without interrupting bus activities.
Functional Description
Switching
The FMIC provides for switching of data from any
input channel to any output channel. This is
accomplished by buffering a single sample of each
channel in an on-chip 384 byte static RAM. Samples
are written into this data RAM in a fixed order and
read out in an order determined by the programming
of the connection memory. An input shift register and
holding latch for each input stream make up the
serial to parallel conversion blocks on the input of
the FMIC and an output holding register an shift
register make up the parallel to serial conversion
blocks on the output of the FMIC.
Data Memory
Data memory is a 384 byte static RAM block which
provides one sample of buffering for each of the 384
channels. An input shift register and holding latch for
each input stream make up the serial to parallel
conversion blocks on the input. Each input channel is
mapped to a unique location in the RAM, as shown
Table 18 - “Data Memory Mapping”.
Data memory can be read and written by the
microprocessor (See “Software Control” for further
details). Note that writing to data memory may be
futile since the contents will be overwritten by
incoming data on the serial input streams.
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