NanoAmp Solutions, Inc.
1982 Zanker Road, San Jose, CA 95112
ph: 408-573-8878, FAX: 408-573-8877
www.nanoamp.com
NT5DS4M32EG
Advance Information
1M × 32 Bits × 4 Banks Double Data Rate Synchronous RAM
With Bi-Directional Data Strobe and DLL
General Overview
The NT5DS4M32EG is 134,217,728 bits of double data rate synchronous dynamic RAM organized as 4 x 1,048,576
bits by 32 I/Os. Synchronous features with Data Strobe allow extremely high performance up to 400Mbps/pin. I/O
transactions are possible on both edges of the clock. Range of operating frequencies, programmable burst length and
programmable latencies allow the device to be useful for a variety of high performance memory system applications.
Features
• VDD = 2.5V±5% , VDDQ = 2.5V±5%
• SSTL_2 compatible inputs/outputs
• 4 banks operation
• MRS cycle with address key programs
• Data I/O transaction on both edges of Data strobe
• 4 DQS (1 DQS/Byte)
• DLL aligns DQ and DQS transaction with Clock
transaction
• Edge aligned data & data strobe output
• Center aligned data & data strobe input
• DM for write masking only
• Auto & self refresh
• 32ms refresh period (4K cycle)
• 144-Ball FBGA package
• Maximum clock frequency up to 200MHz
• Maximum data rate up to 400Mbps/pin
-CAS latency 2,3 (clock)
-Burst length (2, 4, 8 and Full page)
-Burst type (sequential & interleave)
• Full page burst length for sequential burst type
only
• Start address of the full page burst should be even
• All inputs except data & DM are sampled at the ris-
ing edge of the system clock
• Differential clock input(CK & /CK)
Ordering Information
Part Number
Package
Operating
Temperature
Max. Frequency
CL = 3
200MHz
144-Balls
Green FBGA
0 - 70 °C
200MHz
166MHz
CL = 2
111MHz
-
-
Max Data
Rate
400Mbps/pin
400Mbps/pin
333Mbps/pin
Interface
NT5DS4M32EG-5G
NT5DS4M32EG-5
NT5DS4M32EG-6
SSTL_2
Doc # 14-02-045 Rev A ECN 01-1118
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
1
NanoAmp Solutions, Inc.
Figure 1: PIN CONFIGURATION (Top View)
NT5DS4M32EG
Advance Information
1
A
B
C
D
E
F
G
H
J
K
L
M
DQS0
DQ4
DQ6
DQ7
DQ17
DQ19
DQS2
DQ21
DQ22
/CAS
/RAS
/CS
2
DM0
VDDQ
DQ5
VDDQ
DQ16
DQ18
DM2
DQ20
DQ23
/WE
NC
NC
3
VSSQ
NC
VSSQ
VDD
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDD
NC
BA0
4
DQ3
VDDQ
VSSQ
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
BA1
A0
5
DQ2
DQ1
VSSQ
VSSQ
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
A10
A2
A1
6
DQ0
VDDQ
VDD
VSS
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
VDD
A11
A3
7
DQ31
VDDQ
VDD
VSS
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
VDD
A9
A4
8
DQ29
DQ30
VSSQ
VSSQ
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
RFU1
A5
A6
9
DQ28
VDDQ
VSSQ
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
RFU2
A7
10
VSSQ
NC
VSSQ
VDD
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDD
CK
A8/AP
11
DM3
VDDQ
DQ26
VDDQ
DQ15
DQ13
DM1
DQ11
DQ9
NC
/CK
CKE
12
DQS3
DQ27
DQ25
DQ24
DQ14
DQ12
DQS1
DQ10
DQ8
NC
MCL
VREF
NOTE:
1. RFU1 is reserved for A12
2. RFU2 is reserved for BA2
3. VSS Thermal balls are optional
Table 1: PIN Description
CK, /CK
CKE
/CS
/RAS
/CAS
/WE
DQS
DM
RFU
Differential Clock Input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Data Strobe
Data Mask
Reserved for Future Use
BA
0
, BA
1
A
0
~ A
11
DQ0 ~ DQ31
V
DD
V
SS
V
DDQ
V
SSQ
MCL
Bank Select Address
Address Input
Data Input/Output
Power
Ground
Power for DQ’s
Ground for DQ’s
NC
Doc # 14-02-045 Rev A ECN 01-1118
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
2
NanoAmp Solutions, Inc.
NT5DS4M32EG
Advance Information
Table 2: INPUT/OUTPUT FUNCTIONAL DESCRIPTION
Symbol
CK, /CK
#
Type
Input
Function
The differential system clock inputs.
All of the input are sampled on the rising edge of the clock except DQ’s
and DM’s that are sampled on both edges of the DQS.
CKE high activates and CKE low deactivates the internal clock,input buff-
ers and output drivers. By deactivating the clock, CKE low indicates the
Power down mode or Self refresh mode.
/CS enables(registered Low) and disables(registered High) the command
decoder. When /CS is registered High,new commands are ignored but
previous operations are continued.
Latches row addresses on the positive going edge of the CK with /RAS
low. Enables row access & precharge.
Latches Column addresses on the positive going edge of the CK with /
CAS low. Enables column access.
Enables write operation and row precharge. Latches data in starting from /
CAS, /WE active.
Data inputs and outputs are synchronized with both edge of DQS.
DQS0 for DQ0~DQ7, DQS1 for DQ8~DQ15, DQS2 for DQ16~DQ23,
DQS3 for DQ24~DQ31
Data-In mask. Data-In is masked by DM Latency=0 when DM is high in
burst write. DM0 for DQ0 ~ DQ7, DM1 for DQ8 ~ DQ15, DM2 for DQ16 ~
DQ23, DM3 for DQ24 ~ DQ31.
Data inputs and outputs are multiplexed on the same pins.
Select which bank is to be active.
Row,Column addresses are multiplexed on the same pin. Row address :
RA0 ~ RA11, Column address : CA0 ~ CA7. Column address CA8 is used
for auto precharge.
Power and ground for the input buffers and core logic.
Isolated power supply and ground for the output buffers to provide
improved
noise immunity.
Reference voltage for inputs, used for SSTL interface.
This pin is recommend to be left “No Connection” on the device.
Not internally connected
CKE
Input
/CS
/RAS
/CAS
/WE
DQS
0
~ DQS
3
Input
Input
Input
Input
Input, Output
DM
0
~ DM
3
DQ
0
~ DQ
31
BA
0
~ BA
1
A
0
~ A
11
V
DD
, V
SS
V
DDQ
, V
SSQ
V
REF
NC/RFU
MCL
Input
Input, Output
Input
Input
Power Supply
Power Supply
Power Supply
No Connection/
Reserved for future
use
Must Connect Low
# : The timing reference point for the differential clocking is the cross point of CK and /CK.
For any applications using the single ended clocking, apply VREF to /CK pin.
Doc # 14-02-045 Rev A ECN 01-1118
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
3
NanoAmp Solutions, Inc.
NT5DS4M32EG
Advance Information
Figure 2: FUNCTIONAL BLOCK DIAGRAM (1Mbit x 32 I/O x 4 Bank)
32
Input Buffer
LWE
I/O Control
CK, /CK
Bank Select
Data Input Register
Serial to parallel
64
LDMi
1M x 32
2-bit prefetch
Output Buffer
Sense AMP
Refresh Counter
Row Buffer
1M x 32
1M x 32
1M x 32
Row Decoder
64
32
x32
DQi
CK,/CK
Address Register
ADDR
Column Decoder
LRAS
LCBR
Column Buffer
Latency & Burst Length
•
Strobe
Gen.
LCKE
LRAS
LCBR
LWE
Programming Register
DLL
LCAS
LWCBR
LDMi
CK,/CK
Timing Register
CK,/CK
CKE
/CS
/RAS
/CAS
/WE
DMi
Doc # 14-02-045 Rev A ECN 01-1118
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
4
NanoAmp Solutions, Inc.
Figure 3: SIMPLIFIED STATE DIAGRAM
NT5DS4M32EG
Advance Information
SELF
REFRESH
FS
RE
X
FS
RE
MODE
REGISTER
SET
MRS
IDLE
CK
CK
EH
REFA
A UTO
REFRESH
EL
POWER
DOWN
CK
CK
EH
EL
A CT
POWER
DOWN
ROW
A CTIVE
BS
T
WRITE
WRITEA
REA DA
REA D
WRITE
WRITE
WRITEA
WRITEA
WRITE A
PRE
REA D
REA D
REA DA
REA DA
REA D A
POWER
A PPLIED
POWER
ON
PRE
PRE-
CHA RGE
PR
E
Doc # 14-02-045 Rev A ECN 01-1118
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
E
PR
Automatic Sequence
Command Sequence
WRITEA : Write wit h Autoprecharge
READA : Read wit h Autoprecharge
5
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