MT9074
T1/E1/J1 Single Chip Transceiver
Advance Information
Features
•
Combined E1 (PCM 30) and T1 (D4/ESF) framer,
Line Interface Unit (LIU) and link controller with
optional digital framer only mode
In T1 mode the LIU can recover signals attenuated
by up to 36 dB (6000 ft. of 24 AWG cable)
In E1 mode the LIU can recover signals attenuated
by up to 36 dB (2000 m. of 0.65mm cable)
Two HDLCs: FDL and channel 24 in T1 mode,
timeslot 0 (Sa bits) and timeslot 16 in E1 mode
Two-frame elastic buffer in Rx & Tx (T1) directions
Programmable transmit delay through transmit slip
buffer
Low jitter DPLL for clock generation
Enhanced alarms, performance monitoring and
error insertion functions
Intel or Motorola non-multiplexed parallel
microprocessor interface
ST-BUS 2.048 Mbit/s backplane bus for both data
and signaling
Japan Telecom J1 Framing and Yellow Alarm
Hardware data link access
JTAG Boundary Scan
DS5024
ISSUE 5
September 1999
Ordering Information
MT9074AP
MT9074AL
68 Pin PLCC
100 Pin MQFP
-40°C to 85°C
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•
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•
•
•
•
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Description
The MT9074 is a single chip device, operable in
either T1 or E1 mode, integrating either an advanced
T1 (T1 mode) or PCM 30 (E1 mode) framer with a
Line Interface Unit (LIU).
The framer interfaces to a 2.048 Mbit/s backplane
providing selectable data link access with optional
HDLC controllers for either the FDL bits and channel
24 (T1 mode) or S
a
bits and channel 16 (E1 mode).
The LIU interfaces the framer to T1 (T1 mode) or
PCM 30 (E1 mode) transformer-isolated four-wire
line with minimal external components required.
In T1 mode the MT9074 supports D4, ESF and SLC-
96 formats, meeting the latest recommendations
including ITU I.431, AT&T PUB43801, TR-62411,
ANSI T1.102, T1.403 and T1.408. In E1 mode the
MT9074
supports
the
latest
ITU-T
Recommendations including G.703, G.704, G.706,
G.732, G.775, G.796, G.823 for PCM 30, and I.431
for ISDN primary rate. It also supports ETSI ETS 300
011, ETS 300 166 and ETS 300 233.
Applications
•
•
•
•
E1/T1 add/drop multiplexers and channel banks
CO and PBX equipment interfaces
Primary Rate ISDN nodes
Digital Cross-connect Systems (DCS)
TxDL TxDLCLK
TxMF
TxAO TxB TxA
DSTi
CSTi
Tdi
Tdo
Tms
Tclk
Trst
ST-BUS
Interface
IEEE
1149.1
Transmit Framing, Error,
Test Signal Generation and Slip Buffer
Pulse
Generator
Line
Driver
TTIP
TRING
RM
Loop
ST Loop
National
Bit Buffer
Jitter Attenuator
& Clock Control
CAS
Buffer
Clock,Data
Recovery
DG Loop
MT
Loop
PL Loop
R/W/WR
CS
DS/RD
DSTo
CSTo
Rx Equalizer
& Data Slicer
D7~D0
AC4
AC0
Microprocessor
Interface
IRQ
Data Link,
HDLC0
HDLC1
S/FR
BS/LS
OSC1
OSC2
RTIP
RRING
ST-BUS
Interface
Receive Framing, Performance Monitoring,
Alarm Detection, 2 Frame Slip Buffer
RxDLCLK RxDL
RxMF
LOS
RxFP
E1.5o F0b C4b
Figure 1 - Functional Block Diagram
1
MT9074
VSS
OSC2
OSC1
VSS
VDD
S/FR/C1.5i
TxDL
TxLCLK
IC
IC
DS/RD
DSTi
DSTo
CSTi
CSTo
VDD
Advance Information
CS
RESET
IRQ
D0
D1
D2
D3
VSS
IC
INT/MOT
VDD
D4
D5
D6
D7
R/W/WR
AC0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
9
8
7
6
5
4
3
2
1
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
LOS
TxAO
Trst
Tclk
Tms
Tdo
Tdi
GNDATX
TRING
TTIP
VDDATX
VDD
VSS
IC
RxFP
F0b
C4b
E1.5o/C1.5o
NC
NC
NC
NC
NC
NC
DS/RD
DSTi
DSTo
CSTi
CSTo
VDD
VSS
OSC2
OSC1
VSS
VDD
S/FR/
C1.5i
TXDL
TCDLCK
IC
NC
IC
LOS
NC
NC
NC
NC
NC
NC
80
82
48
84
46
86
44
88
42
90
40
92
38
94
36
96
34
98
32
100
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
78
76
74
72
70
68
66
64
62
60
58
56
54
52 50
AC2
AC3
AC4
GNDARx
RTIP
RRING
VDDArx
VDD
VSS
TxA
TxB
RxDCLK
68 PIN PLCC
RxDL
TxMF
RxMF
BS/LS
AC1
NC
NC
CS
RESET
IRQ
D0
D1
D2
D3
VSS
IC
INT/MOT
VDD
D4
D5
D6
D7
R/W/WR
AC0
NC
NC
NC
TxAO
Trst
Tclk
Tms
Tdo
Tdi
GNDATX
TRING
TTIP
VDDATX
VDD
VSS
IC
RxFP
F0b
C4b
E1.5o/C1.5o
NC
2
NC
NC
NC
NC
NC
NC
NC
AC1
AC2
AC3
AC4
GNDARx
RTIP
RRING
VDARx
VDD
VSS
TxA
TxB
100 PIN MQFP (JEDEC MO-112)
Figure 2 - Pin Connections
RXDLCK
RXDL
TxMF
RxMF
BS/L
S
NC
NC
NC
NC
NC
NC
Advance Information
Pin Description
Pin #
68 Pin 100 Pin
PLCC MQFP
1
66
Name
Description
MT9074
OSC1
Oscillator Input.
This pin is either connected via a 20.000 MHz crystal to OSC2
where a crystal is used, or is directly driven when a 20.000 MHz. oscillator is
employed.
Oscillator Output.
Connect a 20.0 MHz crystal between OSC1 and OSC2. Not
suitable for driving other devices.
Negative Power Supply (Input).
Digital ground.
Positive Power Supply (Input).
Digital supply (+5V
±
5%).
Control ST-BUS Output.
CSTo carries serial streams for CAS and CCS
respectively a 2.048 Mbit/s ST-BUS status stream which contains the 30 receive
signalling nibbles (ABCDZZZZ or ZZZZABCD). The most significant nibbles of
each ST-BUS time slot are valid and the least significant nibbles of each ST-BUS
time slot are tristated when control bit MSN (page 01H, address 1AH, bit 1) is set
to 1. If MSN=0, the position of the valid and tristated nibbles are reversed.
Control ST-BUS Input.
CSTi carries serial streams for CAS and CCS respectively
a 2.048 Mbit/s ST-BUS control stream which contains the 30 transmit signalling
nibbles (ABCDXXXX or XXXXABCD) when RPSIG=0. When RPSIG=1 this pin
has no function. The most significant nibbles of each ST-BUS time slot are valid
and the least significant nibbles of each ST-BUS time slot are ignored when control
bit MSN (page 01H, address 1AH, bit 1) is set to 1. If MSN=0, the position of the
valid and ignored nibbles is reversed.
Data ST-BUS Output.
A 2.048 Mbit/s serial stream which contains the 24/30
PCM(T1/E1) or data channels received on the PCM 24/30 (T1/E1) line.
Data ST-BUS Input.
A 2.048 Mbit/s serial stream which contains the 24/30 (T1/
E1)PCM or data channels to be transmitted on the PCM 24/30 (T1/E1)line.
Data/Read Strobe (Input).
In Motorola mode (DS), this input is the active low data strobe of the
microprocessor interface.
In Intel mode (RD), this input is the active low read strobe of the microprocessor
interface.
Chip Select (Input).
This active low input enables the non-multiplexed parallel
microprocessor interface of the MT9074. When CS is set to high, the
microprocessor interface is idle and all bus I/O pins will be in a high impedance
state.
RESET (Input).
This active low input puts the MT9074 in a reset condition. RESET
should be set to high for normal operation. The MT9074 should be reset after
power-up. The RESET pin must be held low for a minimum of 1µsec. to reset the
device properly.
Interrupt Request (Output).
A low on this output pin indicates that an interrupt
request is presented. IRQ is an open drain output that should be connected to V
DD
through a pull-up resistor. An active low CS signal is not required for this pin to
function.
Data 0 to Data 3 (Three-state I/O).
These signals combined with D4-D7 form the
bidirectional data bus of the microprocessor interface (D0 is the least significant
bit).
2
3
4
5
67
68
69
70
OSC2
V
SS
V
DD
CSTo
6
71
CSTi
7
8
9
72
73
74
DSTo
DSTi
DS/RD
10
83
CS
11
84
RESET
12
85
IRQ
13 -
16
86-89
D0 - D3
3
MT9074
Pin Description
Pin #
68 Pin 100 Pin
PLCC MQFP
17
18
19
90
91
92
Name
Description
Advance Information
Vss
IC
INT/MOT
Negative Power Supply (Input).
Digital ground.
Internal Connection.
Tie to Vss (ground) for normal operation.
Intel/Motorola Mode Selection (Input).A
high on this pin configures the
processor interface for the Intel parallel non-multiplexed bus type. A low configures
the processor interface for the Motorola parallel non-multiplexed type.
Positive Power Supply (Input).
Digital supply (+5V± 5%).
Data 4 to Data 7 (Three-state I/O).
These signals combined with D0-D3 form the
bidirectional data bus of the parallel processor interface (D7 is the most significant
bit).
Read/Write/Write Strobe (Input). In Motorola mode (R/W), this input controls the
direction of the data bus D[0:7] during a microprocessor access. When R/W is
high, the parallel processor is reading data from the MT9074. When low, the
parallel processor is writing data to the MT9074. For Intel mode (WR), this active
low write strobe configures the data bus lines as output.
20
21 -
24
25
93
94-97
VDD
D4 - D7
98
R/W/WR
26 -
30
31
32
33
99, 8-11 AC0 - AC4 Address/Control 0 to 4 (Inputs).
Address and control inputs for the non-
multiplexed parallel processor interface. AC0 is the least significant input.
12
13
14
GND
ARx
RTIP
RRING
Receive Analog Ground (Input).
Analog ground for the LIU receiver.
Receive TIP and RING (Input).
Differential inputs for the receive line signal - must
be transformer coupled (See Figure 5). In digital framer mode these are TTL level
inputs that connect to the digital outputs of a receiver. If the receiver serial data
output is NRZ connect that output to RTIP. If the receiver data output is split phase
unipolar signal connect one signal to RTIP and the complementary signal to
RRING.
Receive Analog Power Supply (Input).
Analog supply for the LIU receiver (+5V
±
5%).
Positive Power Supply (Input).
Digital supply (+5V
±
5%).
Negative Power Supply (Input).
Digital ground.
Transmit A (Output).
When the internal LIU is disabled (digital framer only
mode), if control bit NRZ=1, and NRZ output data is clocked out on pin TxA with
the rising edge of C1.50 (TxB has no function when NRZ format is selected). If
NRZ=0, pins TxA and TxB are a complementary pair of signals that output digital
dual-rail clocked out with the rising edge of C1.50.
Transmit B (Output).
When the internal LIU is disabled and control bit NRZ=0,
pins TxA and TxB are a complementary pair of signals that output digital dual-rail
data clocked out with the rising edge of C1.50.
34
35
36
37
15
16
17
18
VDD
ARx
VDD
VSS
TxA
38
19
TxB
39
20
RxDLCLK Data Link Clock (Output).
A gapped clock signal derived from the extracted clock
from the line clock, available for an external device to clock in RxDL data (at 4, 8,
12, 16 or 20 kHz) on the rising edge.
RxDL
TxMF
Receive Data Link (Output).
A serial bit stream containing received line data after
zero code suppression. This data is clocked out with the rising edge of E1.5o.
Transmit Multiframe Boundary (Input).
An active low input used to set the
transmit multiframe boundary (CAS or CRC multiframe). The MT9074 will generate
its own multiframe if this pin is held high. This input is usually pulled high for most
applications.
40
41
21
22
4
Advance Information
Pin Description
Pin #
68 Pin 100 Pin
PLCC MQFP
42
23
Name
Description
MT9074
RxMF
Receive Multiframe Boundary (Output).
An output pulse delimiting the received
multiframe boundary. The next frame output on the data stream (DSTo) is basic
frame zero on the T1 or PCM 30 link. In E1 mode this receive multiframe signal
can be related to either the receive CRC multiframe (page 01H, address 17H, bit 6,
MFSEL=1) or the receive signalling multiframe (MFSEL=0).
Bus/Line Synchronization Mode Selection (Input).
If high, C4b and F0b will be
inputs; if low, C4b and F0b will be outputs.
43
44
24
32
BS/LS
E1.5o/C1.5o 2.048 MHz in E1 mode or 1.544MHz in T1 mode, Extracted Clock (Output).
If the internal L/U is enabled, this output is the clock extracted from the received
signal and used internally to clock in data received on RTIP and RRING. If the
internal LIU is disabled (digital framer mode), this output is a 1.544MHz clock
(T1) C1.5o or a 2.048 MHz clock C2o which clocks out the transmit digital data
TXA, TXB.
C4b
4.096 MHz System Clock (Input/Output).
C4b is the clock for the ST-BUS
sections and transmit serial PCM data of the MT9074. In the free-run (S/FR=0) or
line synchronous mode (S/FR=1 and BS/LS=0) this signal is an output, while in
bus synchronous mode (S/FR=1) this signal is an input clock which is phase-
locked to the extracted clock (E1.5o).
Frame Pulse (Input/Output).
This is the ST-BUS frame synchronization signal,
which delimits the 32 channel frame of CSTi, CSTo, DSTi, DSTo and the PCM30
link. In the free-run (S/FR=0) or line synchronous mode (S/FR=1 and BS/LS=0)
this signal is an output, while in the line synchrounous mode (S/FR=1 and BS/
LS=0) this signal is an input.
Receive Frame Pulse (Output).
An 8kHz pulse signal, which is low for one
extracted clock period. This signal is synchronized to the receive DS1 or PCM 30
basic frame boundary.
Internal Connection.
Must be left open for normal operation.
Negative Power Supply (Input).
Digital ground.
Positive Power Supply (Input).
Digital supply (+5V
±
5%).
Transmit Analog Power Supply (Input).
Analog supply for the LIU transmitter
(+5V
±
5% 10%)).
Transmit TIP and RING (Outputs).
Differential outputs for the transmit DS1 line
signal - must be transformer coupled (See Figure 5).
Transmit Analog Ground (Input).
Analog ground for the LIU transmitter.
IEEE 1149.1 Test Data Input.
If not used, this pin should be pulled high.
IEEE 1149.1 Test Data Output.
If not used, this pin should be left unconnected.
IEEE 1149.1 Test Mode Selection (Input).
If not used, this pin should be pulled
high.
IEEE 1149.1 Test Clock Signal (Input).
If not used, this pin should be pulled high.
IEEE 1149.1 Reset Signal (Input).
If not used, this pin should be held low.
Transmit All Ones (Input).High
- TTIP, TRING will transmit data normally. Low -
TTIP, TRING will transmit an all ones signal.
45
33
46
34
F0b
47
35
RxFP
48
49
50
51
52
53
54
55
56
57
58
59
60
36
37
38
39
40
41
42
43
44
45
46
47
48
IC
V
SS
V
DD
VDD
ATx
TTIP
TRING
GND
ATx
Tdi
Tdo
Tms
Tclk
Trst
TxAO
5
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