®
CMOS
MT90710
High-Speed Isochronous Multiplexer
Preliminary Information
Features
•
•
•
•
•
•
•
•
•
•
Multiplexes eight 2.048 Mbit/s, ST-BUS links
onto one serial high-speed 20.48 Mbit/s link
15.808 Mbit/s clear bandwidth transport
Two 8 kbit/s and one 32 kbit/s oversampled
signalling channels
Embedded system timing and frame
synchronization
Frame buffer control signals generated on-chip
Check-sum generated on multiplexed frame
Remote synchronization indication
Both master and slave timing mode operation
On-chip reference generation for slave mode
synchronization
4B/5B data encoding/decoding
MT90710AP
ISSUE 1
January 1995
Ordering Information
84 Pin PLCC
0 °C to +70 °C
Description
The High-Speed Isochronous Multiplexer integrated
circuit multiplexes up to eight Serial Telecom
(ST-BUS) links onto a single 20 MHz loop to facilitate
point-to-point data transport requirements. The
MT90710 connects easily with standard Fiber Optic
interfaces to form a complete electric to photonic
conversion circuit. Optical transmission allows large
bandwidth inter-shelf or, in distributed systems,
inter-node communication by eliminating multiple
data buses, cable inter-connect and attendant driver
interfaces. The final result is a simple physical
interface free of the radiated emissions and
background
noise
susceptibility
problems
encountered in copper-wired environments.
Applications
•
•
•
Fibre distributed sytems
Backplane concentrators
Local Area Networks (LANs)
STi0
STi5
STi6A
STi6B
STi7
DIN8K0
DIN8K1
DIN32K
STo0
STo5
STo6A
STo6B
STo7
DOUT8K0
DOUT8K1
DOUT32K
TRANSMIT
To Transmit Driver
Amplifier and Fiber
Driver Transducer
TxDATA
MODE0
MODE1
MODE2
F0b
C4b
E20i
RLED
LLED
C20o
POR
RESET
C4REFo
C4o
C40i
MUX
Overhead
Checksum
Frame Sync
4B/5B &
NRZI
Encode
PISO
Control
RECEIVE
DEMUX
Overhead
Extract &
Insert
Error Check
Frame Alignment & Buffer
External Memory Control
NRZI Decode
Sync Detect
4B/5B Decode
From Receive Pin Diode,
Pre-amp and Post-amp
Circuits
SIPO
RxDATA
Signals to
External PLL
FBDATA0
FBADDR0
FBADDR7
FBDATA7
Figure 1 - Functional Block Diagram
5-3
FBWE
FBOE
MT90710
Preliminary Information
DOUT32K
RxDATA
TxDATA
MODE0
MODE1
MODE2
FBWE
FBOE
RLED
STo1
STo4
STo3
STo2
STo0
VDD
52
50
48
46
44
42
40
38
36
VDD
POR
FBDATA7
C4b
FBDATA6
FBDATA5
DIN8K0
FBDATA4
DIN32K
VDD
VSS
FBDATA3
STi0
FBDATA2
DIN8K1
FBDATA1
LLED
FBDATA0
RESET
IC
VDD
54
56
58
60
62
64
66
68
70
72
34
VDD
VSS
VSS
F0b
NC
IC
32
30
28
26
24
NC
VSS
NC
E20i
STi7
STi6B
STi6A
STi5
STi4
STi3
VDD
VSS
STi2
STi1
C40i
NC
NC
NC
C4REFo
C4o
VSS
84 PIN PLCC
22
20
18
16
14
76
78
80
82
84
74
STo6B
STo6A
VSS
VSS
VDD
10
12
4
6
2
8
FBADDR0
FBADDR1
FBADDR2
FBADDR3
FBADDR4
FBADDR5
FBADDR6
FBADDR7
DOUT8K0
DOUT8K1
C20o
STo7
Figure 2 - Pin Connections
Pin Description
Pin #
1
2
3
Name
V
SS
V
DD
STo7
Description
Power Supply Ground.
Nominally 0 volts.
Positive Power Supply.
Nominally 5 volts.
Serial, 32 Channel, 2.048 Mb/s Link 7 (Output Type 3).
Only channels 9 - 31 are
available for user data transfer (1.474 Mb/s). Channels 0 - 8 (0.576 Mb/s) are reserved
for access to fiber overhead information. Output is active only when the receiver
detects the synchronization pattern on RxDATA input stream; output is high impedance
during loss of synchronization.
Asynchronous 8 kHz Signal 0 (Output Type 3).
Sourced from the far-end DIN8K0
input.
Asynchronous 8 kHz Signal 1 (Output Type 3).
Sourced from the far-end DIN8K1
input.
20.48 MHz Clock (Output Type 3).
Derived from transmit PLL 40.96 MHz clock divided
by 2 (see pin 18). Made available for system use.
No Internal Connection.
Frame Buffer RAM Address Bit 7 (Output Type 2).
Serial, 32 Channel, 2.048 Mb/s Link 6A (Output Type 3).
Output is active only when
the receiver detects the synchronization pattern on RxDATA input stream; output is high
impedance during loss of synchronization.
4
5
6
7
8
9
DOUT8K0
DOUT8K1
C20o
NC
FBADDR7
STo6A
5-4
STo5
VDD
NC
NC
Preliminary Information
Pin Description
Pin #
10
Name
STo5
Description
MT90710
Serial, 32 Channel, 2.048 Mb/s Link 5 (Output Type 3).
Output is active only when
the receiver detects the synchronization pattern on RxDATA input stream; output is high
impedance during loss of synchronization.
Positive Power Supply.
Nominally 5 volts.
Power Supply Ground.
Nominally 0 volts.
4.096 MHz Clock (Output Type 3).
Used by the transmit PLL. This clock is the input
C40i (40.96MHz, see pin 18) master clock divided by 10 (inverted) and is fed back to
the external PLL circuit as a reference.
4.096 MHz Reference Clock (Output Type 3).
Used by transmit PLL. When in control-
ler mode this clock is derived from the system C4b (4.096 MHz) clock input (see pin
57). When in peripheral mode this clock is extracted from the receive data on the fiber
port.
No Internal Connection.
Transmit 40.96 MHz Clock (Input Type 2).
Derived from the transmit PLL. This is the
master clock used by the device.
Serial, 32 Channel, 2.048 Mb/s Link 1 (Input Type 1).
Serial, 32 Channel, 2.048 Mb/s Link 2 (Input Type 1).
Power Supply Ground.
Nominally 0 volts.
Positive Power Supply.
Nominally 5 volts.
Serial, 32 Channel, 2.048 Mb/s Link 3 (Input Type 1).
Serial, 32 Channel, 2.048 Mb/s Link 4 (Input Type 1).
Serial, 32 Channel, 2.048 Mb/s Link 5 (Input Type 1).
Serial, 32 Channel, 2.048 Mb/s Link 6A (Input Type 1).
Serial, 32 Channel, 2.048 Mb/s Link 6B (Input Type 1).
Serial, 32 Channel, 2.048 Mb/s Link 7 (Input Type 1).
Only channels 9 - 31 are avail-
able for user data transfer (1.472 Mb/s). Data input on channels 0 - 8 (0.576 Mb/s) is
ignored by the device. This bandwidth is reserved for fiber overhead information.
Receiver 20.96 MHz Clock (Input Type 2).
Extracted clock from the receive data
stream. Divided internally by 5 and phase corrected to frame synch pattern to produce
internal 2.048 MHz data clock for parsing the receive STi streams.
No Internal Connection.
Power Supply Ground.
Nominally 0 volts.
No Internal Connection.
Positive Power Supply.
Nominally 5 volts.
No Internal Connection.
Receive 4B/5B, NRZI Encoded Serial Data (Input Type 1).
"Remote Sync" LED Driver (Open Collector, Output Type 3).
Drives the "Remote
Sync" LED on/off at approximately a 4 Hz rate when the remote interface is not syn-
chronized. Active only when the local interface is synchronized.
Frame Buffer Ram Enable (Output Type 2).
Generates a low going strobe during
valid RAM read access.
5-5
11
12
13
V
DD
V
SS
C4o
14
C4REFo
15,16,
17
18
19
20
21
22
23
24
25
26
27
28
NC
C40i
STi1
STi2
V
SS
V
DD
STi3
STi4
STi5
STi6A
STi6B
STi7
29
E20i
30
31
32
33
34
35
36
NC
V
SS
NC
V
DD
NC
RxDATA
RLED
37
FBOE
MT90710
Pin Description
Pin #
38
39
40
41
Name
MODE2
MODE1
MODE0
STo0
Description
Operating Mode Select 2 (Input Type 1).
See Table 1.
Operating Mode Select 1 (Input Type 1).
See Table 1.
Operating Mode Select 0 (Input Type 1).
See Table 1.
Preliminary Information
Serial, 32 Channel, 2.048 Mb/s link 0 (Output Type 3).
Output is active only when
receiver detects the synchronization pattern on RxDATA input stream; output is high
impedance during loss of synchronization.
Positive Power Supply.
Nominally 5 volts.
Power Supply Ground.
Nominally 0 volts.
Serial, 32 Channel, 2.048 Mb/s link 2 (Output Type 3).
Output active only when
receiver detects the synchronization pattern on RxDATA input stream; high impedance
output during loss of synchronization.
Serial, 32 Channel, 2.048 Mb/s link 3 (Output Type 3).
Output active only when
receiver detects the synchronization pattern on RxDATA input stream; high impedance
output during loss of synchronization.
Serial, 32 Channel, 2.048 Mb/s link 4 (Output Type 3).
Output active only when
receiver detects the synchronization pattern on RxDATA input stream; high impedance
output during loss of synchronization.
Frame Buffer RAM Write Enable (Output Type 2).
Generates a low going strobe dur-
ing valid RAM write access.
Serial, 32 Channel, 2.048 Mb/s link 1 (Output Type 3).
Output active only when
receiver detects the synchronization pattern on RxDATA input stream; high impedance
output during loss of synchronization.
System 8 kHz Reference Frame Pulse
(Bi-directional;
Input and Output Types 3).
When in controller mode this is an input accepting the system reference pulse. In
peripheral mode this is an output supplying the system an 8 kHz reference frame pulse.
Asynchronous 32 kHz Signal 1 (Open Collector, Output Type 3).
Sourced from the
far-end DIN32K input.
Transmit 4B/5B, NRZI Encoded Serial Data (Output Type 3).
Power Supply Ground.
Nominally 0 volts.
Internally Connected (Output Type 1).
Drives continuous logic 1. Leave open circuit.
Positive Power Supply.
Nominally 5 volts.
Power On Reset (Input Type 2).
Active low.
Frame Buffer Data Bit 7 (Bidirectional; Input Type 1 and Output Type 2).
Data bit 7.
4.096 MHz Reference Clock (Bidirectional; Input and Output Types 3).
Input used
by PLL in controller mode and derived from the system. In peripheral mode this is an
output supplying the system 4.096 MHz reference clock.
Frame Buffer Data Bit 6 (Bidirectional; Input Type 1 and Output Type 2).
Data bit 6.
Frame Buffer Data Bit 5 (Bidirectional; Input Type 1 and Output Type 2).
Data bit 5.
Asynchronous 8 kHz Signal 0 (Input Type 1).
Transmitted to the far-end DOUT8K0
output.
Frame Buffer Data Bit 4 (Bidirectional; Input Type 1 and Output Type 2).
Data bit 4.
42
43
44
V
DD
V
SS
STo2
45
STo3
46
STo4
47
48
FBWE
STo1
49
F0b
50
51
52
53
54
55
56
57
DOUT32K
TxDATA
V
SS
IC
V
DD
POR
FBDATA7
C4b
58
59
60
61
FBDATA6
FBDATA5
DIN8K0
FBDATA4
5-6
Preliminary Information
Pin Description
Pin #
62
63
64
65
66
67
68
69
70
Name
DIN32K
V
DD
V
SS
FBDATA3
STi0
FBDATA2
DIN8K1
FBDATA1
LLED
Description
MT90710
Asynchronous 32 kHz Signal (Input Type 1).
Transmitted to the far-end DOUT32K
output.
Positive Power Supply.
Nominally 5 volts.
Power Supply Ground.
Nominally 0 volts.
Frame Buffer Data Bit 3 (Bidirectional; Input Type 1 and Output Type 2).
Data bit 3.
Serial, 32 Channel, 2.048 Mb/s Link 0 (Input Type 1).
Frame Buffer Data Bit 2 (Bidirectional; Input Type 1 and Output Type 2).
Data bit 2.
Asynchronous 8 kHz Signal 1 (Input Type 1).
Transmitted to the far-end DOUT8K1
output.
Frame Buffer Data Bit 1 (Bidirectional; Input Type 1 and Output Type 2).
Data bit 1.
"Local Sync" LED Driver (Open Collector, Output Type 2).
Drives the "Local Sync"
LED on/off at approximately a 4 Hz rate when the local interface is not in
synchronization.
Frame Buffer Data Bit 0 (Bidirectional; Input Type 1 and Output Type 2).
Data bit 0.
Reset Control (Input Type 1).
Internally Connected.
Positive Power Supply.
Nominally 5 volts.
No Internal Connection.
Power Supply Ground.
Nominally 0 volts.
Frame Buffer RAM Address Bit 0 (Output Type 2).
Frame Buffer RAM Address Bit 1 (Output Type 2).
Frame Buffer RAM Address Bit 2 (Output Type 2).
Frame Buffer RAM Address Bit 3 (Output Type 2).
Frame Buffer RAM Address Bit 4 (Output Type 2).
Frame Buffer RAM Address Bit 5 (Output Type 2).
Frame Buffer RAM Address Bit 6 (Output Type 2).
Serial, 32 Channel, 2.048 Mb/s Link 6B (Output Type 3).
Output active only when
receiver detects the synchronization pattern on RxDATA input stream; high impedance
output during loss of synchronization.
71
72
73
74
75
76
77
78
79
80
81
82
83
84
FBDATA0
RESET
IC
V
DD
NC
V
SS
FBADDR0
FBADDR1
FBADDR2
FBADDR3
FBADDR4
FBADDR5
FBADDR6
STo6B
Notes:
All unused inputs should be connected to logic high or low unless otherwise stated. All outputs should be left open circuit when not used.
All output types are CMOS with CMOS logic levels (see DC Electrical Characteristics for Type drive capability).
Input Type 1 has TTL compatible logic levels, Type 2 has CMOS compatible logic levels and Type 3 has TTL Schmitt trigger compatible
logic levels (see DC Electrical Characteristics).
Overview
The MT90710 multiplexes multiple Serial Telecom
(ST-BUS timing, Figure 7) links onto a single 20 MHz
loop to facilitate point-to-point data transport
requirements. The MT90710 connects easily with
standard Fiber Optic interfaces to form a complete
electric to photonic conversion circuit. Optical
transmission allows large bandwidth inter-shelf or, in
distributed systems, inter-node communication by
eliminating multiple data busses, cable inter-connect
and the attendant driver interfaces. The final result is
a simple physical interface free of the radiated
emissions and background noise susceptibility
problems
encountered
in
copper-wired
environments.
5-7
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